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| author | Jean-Jacques Hiblot <jjhiblot@ti.com> | 2018-01-30 16:01:33 +0100 |
|---|---|---|
| committer | Jaehoon Chung <jh80.chung@samsung.com> | 2018-02-19 16:58:54 +0900 |
| commit | 8fc238bfada16d61dee4240de2d49f38a6a6f941 (patch) | |
| tree | 479a95aaccb99e39504f864fe07e57778373253c /drivers/mmc/omap_hsmmc.c | |
| parent | b59448170934094570a497ff7c5b4b2e94cff5a2 (diff) | |
| download | u-boot-8fc238bfada16d61dee4240de2d49f38a6a6f941.zip u-boot-8fc238bfada16d61dee4240de2d49f38a6a6f941.tar.gz u-boot-8fc238bfada16d61dee4240de2d49f38a6a6f941.tar.bz2 | |
mmc: omap_hsmmc: set MMC mode in the UHSMS bit field
Use the timing parameter set in the MMC core to set the
mode in UHSMS bit field. This is in preparation for
adding HS200 support in omap hsmmc driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Diffstat (limited to 'drivers/mmc/omap_hsmmc.c')
| -rw-r--r-- | drivers/mmc/omap_hsmmc.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 5141bf6..c6b74a1 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -76,6 +76,7 @@ struct omap_hsmmc_data { #endif #if CONFIG_IS_ENABLED(DM_MMC) uint iov; + enum bus_mode mode; #endif u8 controller_flags; #ifndef CONFIG_OMAP34XX @@ -258,6 +259,48 @@ void mmc_init_stream(struct hsmmc *mmc_base) } #if CONFIG_IS_ENABLED(DM_MMC) +static void omap_hsmmc_set_timing(struct mmc *mmc) +{ + u32 val; + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + + mmc_base = priv->base_addr; + + val = readl(&mmc_base->ac12); + val &= ~AC12_UHSMC_MASK; + priv->mode = mmc->selected_mode; + + switch (priv->mode) { + case MMC_HS_200: + case UHS_SDR104: + val |= AC12_UHSMC_SDR104; + break; + case UHS_SDR50: + val |= AC12_UHSMC_SDR50; + break; + case MMC_DDR_52: + case UHS_DDR50: + val |= AC12_UHSMC_DDR50; + break; + case SD_HS: + case MMC_HS_52: + case UHS_SDR25: + val |= AC12_UHSMC_SDR25; + break; + case MMC_LEGACY: + case MMC_HS: + case SD_LEGACY: + case UHS_SDR12: + val |= AC12_UHSMC_SDR12; + break; + default: + val |= AC12_UHSMC_RES; + break; + } + writel(val, &mmc_base->ac12); +} + static void omap_hsmmc_conf_bus_power(struct mmc *mmc) { struct hsmmc *mmc_base; @@ -928,6 +971,10 @@ static int omap_hsmmc_set_ios(struct udevice *dev) if (priv->clock != mmc->clock) omap_hsmmc_set_clock(mmc); +#if CONFIG_IS_ENABLED(DM_MMC) + if (priv->mode != mmc->selected_mode) + omap_hsmmc_set_timing(mmc); +#endif return 0; } |