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| author | Simon Glass <sjg@chromium.org> | 2020-07-07 21:32:19 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-07-17 14:32:24 +0800 |
| commit | 4916f4586eab7941f38a89e4dacd103af1c4105f (patch) | |
| tree | 0abebe14dc6594fdeffc71617026250afdc88501 /drivers/gpio/intel_gpio.c | |
| parent | 54bcca29737f8de2598b4a3f8f503290bd49eec0 (diff) | |
| download | u-boot-4916f4586eab7941f38a89e4dacd103af1c4105f.zip u-boot-4916f4586eab7941f38a89e4dacd103af1c4105f.tar.gz u-boot-4916f4586eab7941f38a89e4dacd103af1c4105f.tar.bz2 | |
x86: pinctrl: Add a way to get the pinctrl reg address
At present we can query the offset of a pinctrl register within the p2sb.
For ACPI we need to get the actual address of the register. Add a function
to handle this and rename the old one to more accurately reflect its
purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Diffstat (limited to 'drivers/gpio/intel_gpio.c')
| -rw-r--r-- | drivers/gpio/intel_gpio.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c index 711fea1..b4d5be9 100644 --- a/drivers/gpio/intel_gpio.c +++ b/drivers/gpio/intel_gpio.c @@ -24,7 +24,9 @@ static int intel_gpio_direction_input(struct udevice *dev, uint offset) { struct udevice *pinctrl = dev_get_parent(dev); - uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset); + uint config_offset; + + config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset); pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE | @@ -38,7 +40,9 @@ static int intel_gpio_direction_output(struct udevice *dev, uint offset, int value) { struct udevice *pinctrl = dev_get_parent(dev); - uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset); + uint config_offset; + + config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset); pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE | @@ -68,10 +72,13 @@ static int intel_gpio_get_value(struct udevice *dev, uint offset) return 0; } -static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value) +static int intel_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) { struct udevice *pinctrl = dev_get_parent(dev); - uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset); + uint config_offset; + + config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset); pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE, value ? PAD_CFG0_TX_STATE : 0); |