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authorTom Rini <trini@konsulko.com>2022-04-04 10:45:33 -0400
committerTom Rini <trini@konsulko.com>2022-04-04 10:48:44 -0400
commit01f1ab67f38882dc7665a0a6eca4bbeba6d84f81 (patch)
tree31b1febefe82731d94571f7442877c039efb602c /drivers/gpio/gpio_slg7xl45106.c
parente4b6ebd3de982ae7185dbf689a030e73fd06e0d2 (diff)
parent8221c52d88fbe84ca9692dc23827e21403c952e8 (diff)
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Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/gpio/gpio_slg7xl45106.c')
-rw-r--r--drivers/gpio/gpio_slg7xl45106.c115
1 files changed, 115 insertions, 0 deletions
diff --git a/drivers/gpio/gpio_slg7xl45106.c b/drivers/gpio/gpio_slg7xl45106.c
new file mode 100644
index 0000000..2cbf748
--- /dev/null
+++ b/drivers/gpio/gpio_slg7xl45106.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * slg7xl45106_i2c_gpo driver
+ *
+ * Copyright (C) 2021 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+
+#define SLG7XL45106_REG 0xdb
+
+static int slg7xl45106_i2c_gpo_direction_input(struct udevice *dev,
+ unsigned int offset)
+{
+ return 0;
+}
+
+static int slg7xl45106_i2c_gpo_xlate(struct udevice *dev,
+ struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ desc->offset = (unsigned int)args->args[0];
+
+ return 0;
+}
+
+static int slg7xl45106_i2c_gpo_set_value(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ int ret;
+ u8 val;
+
+ ret = dm_i2c_read(dev, SLG7XL45106_REG, &val, 1);
+ if (ret)
+ return ret;
+
+ if (value)
+ val |= BIT(offset);
+ else
+ val &= ~BIT(offset);
+
+ return dm_i2c_write(dev, SLG7XL45106_REG, &val, 1);
+}
+
+static int slg7xl45106_i2c_gpo_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ return slg7xl45106_i2c_gpo_set_value(dev, offset, value);
+}
+
+static int slg7xl45106_i2c_gpo_get_value(struct udevice *dev,
+ unsigned int offset)
+{
+ int ret;
+ u8 val;
+
+ ret = dm_i2c_read(dev, SLG7XL45106_REG, &val, 1);
+ if (ret)
+ return ret;
+
+ return !!(val & BIT(offset));
+}
+
+static int slg7xl45106_i2c_gpo_get_function(struct udevice *dev,
+ unsigned int offset)
+{
+ return GPIOF_OUTPUT;
+}
+
+static const struct dm_gpio_ops slg7xl45106_i2c_gpo_ops = {
+ .direction_input = slg7xl45106_i2c_gpo_direction_input,
+ .direction_output = slg7xl45106_i2c_gpo_direction_output,
+ .get_value = slg7xl45106_i2c_gpo_get_value,
+ .set_value = slg7xl45106_i2c_gpo_set_value,
+ .get_function = slg7xl45106_i2c_gpo_get_function,
+ .xlate = slg7xl45106_i2c_gpo_xlate,
+};
+
+static int slg7xl45106_i2c_gpo_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const void *label_ptr;
+
+ label_ptr = dev_read_prop(dev, "label", NULL);
+ if (label_ptr) {
+ uc_priv->bank_name = strdup(label_ptr);
+ if (!uc_priv->bank_name)
+ return -ENOMEM;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
+
+ uc_priv->gpio_count = 8;
+
+ return 0;
+}
+
+static const struct udevice_id slg7xl45106_i2c_gpo_ids[] = {
+ { .compatible = "dlg,slg7xl45106",},
+ { }
+};
+
+U_BOOT_DRIVER(slg7xl45106_i2c_gpo) = {
+ .name = "slg7xl45106_i2c_gpo",
+ .id = UCLASS_GPIO,
+ .ops = &slg7xl45106_i2c_gpo_ops,
+ .of_match = slg7xl45106_i2c_gpo_ids,
+ .probe = slg7xl45106_i2c_gpo_probe,
+};