diff options
| author | York Sun <yorksun@freescale.com> | 2014-02-10 13:59:42 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-21 11:06:13 -0500 |
| commit | 4e5b1bd0dff216b00d7ce9a5201dfe173805a06c (patch) | |
| tree | d8f8e7ffda3f504d4d98b6f494f0c73eed1196fc /drivers/ddr/fsl/ctrl_regs.c | |
| parent | 9c89614d3f1ea510d7fcb4a2b438fb3e0d58392c (diff) | |
| download | u-boot-4e5b1bd0dff216b00d7ce9a5201dfe173805a06c.zip u-boot-4e5b1bd0dff216b00d7ce9a5201dfe173805a06c.tar.gz u-boot-4e5b1bd0dff216b00d7ce9a5201dfe173805a06c.tar.bz2 | |
driver/ddr: Change Freescale ARM DDR driver to support both big and little endian
Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/ctrl_regs.c')
| -rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 6bf22cf..5acbc73 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -25,8 +25,8 @@ static u32 fsl_ddr_get_version(void) u32 ver_major_minor_errata; ddr = (void *)_DDR_ADDR; - ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; - ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; + ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; return ver_major_minor_errata; } |