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| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-04-27 12:27:21 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-06-16 16:10:44 +0800 |
| commit | ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4 (patch) | |
| tree | fb14185e5c4c674453af6f93ec7d18a12ef5b878 /drivers/ddr/altera | |
| parent | f70e00fa7da69d16379c0b3526b793be45cd055d (diff) | |
| download | u-boot-ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4.zip u-boot-ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4.tar.gz u-boot-ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4.tar.bz2 | |
ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'drivers/ddr/altera')
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 7460f8c..07a0f9f 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -53,7 +53,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0xF #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f |