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| author | Stefan Roese <sr@denx.de> | 2022-09-02 14:10:46 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2022-09-18 10:26:33 +0200 |
| commit | 29caf9305b6fafe8f6d6b18fa1f825dff8686e61 (patch) | |
| tree | 6530f6a2373b7af6fb4fdceca823b21f7c79ed7f /drivers/ddr/altera | |
| parent | 881d4108257a45ac890ef27c523783dbe401e462 (diff) | |
| download | u-boot-29caf9305b6fafe8f6d6b18fa1f825dff8686e61.zip u-boot-29caf9305b6fafe8f6d6b18fa1f825dff8686e61.tar.gz u-boot-29caf9305b6fafe8f6d6b18fa1f825dff8686e61.tar.bz2 | |
cyclic: Use schedule() instead of WATCHDOG_RESET()
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
Diffstat (limited to 'drivers/ddr/altera')
| -rw-r--r-- | drivers/ddr/altera/sdram_arria10.c | 4 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_n5x.c | 4 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 4a8f8de..8ef5fa4 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -671,7 +671,7 @@ static int of_sdram_firewall_setup(const void *blob) int ddr_calibration_sequence(void) { - WATCHDOG_RESET(); + schedule(); /* Check to see if SDRAM cal was success */ if (sdram_startup()) { @@ -681,7 +681,7 @@ int ddr_calibration_sequence(void) puts("DDRCAL: Success\n"); - WATCHDOG_RESET(); + schedule(); /* initialize the MMR register */ sdram_mmr_init(); diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 737a4e2..d903944 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -517,7 +517,7 @@ static int ensure_retry_procedure_complete(phys_addr_t umctl2_base) DDR4_CRCPARSTAT_CMD_IN_ERR_WINDOW; udelay(1); - WATCHDOG_RESET(); + schedule(); } return 0; @@ -1349,7 +1349,7 @@ static int ddr_post_handoff_config(phys_addr_t umctl2_base, } udelay(1); - WATCHDOG_RESET(); + schedule(); /* Polling until SDRAM entered normal operating mode */ value = readl(umctl2_base + DDR4_STAT_OFFSET) & diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 9b1710c..4716abf 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -161,7 +161,7 @@ void sdram_init_ecc_bits(struct bd_info *bd) sdram_clear_mem(start_addr, size_init); size -= size_init; start_addr += size_init; - WATCHDOG_RESET(); + schedule(); } bank++; |