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| author | Atish Patra <atish.patra@wdc.com> | 2019-02-25 08:15:14 +0000 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-02-27 09:12:33 +0800 |
| commit | 007056f495c9fc5c544f71762f874a19a9b004a3 (patch) | |
| tree | 431578d271f4c2e26aeb84363b0f0fa5dfde254b /drivers/cpu/riscv_cpu.c | |
| parent | ee0633ef8b027960bd53ab62abb6f6fc25b1c66b (diff) | |
| download | u-boot-007056f495c9fc5c544f71762f874a19a9b004a3.zip u-boot-007056f495c9fc5c544f71762f874a19a9b004a3.tar.gz u-boot-007056f495c9fc5c544f71762f874a19a9b004a3.tar.bz2 | |
cpu: Bind timer driver for boot hart
Currently, timer driver is bound only for hart0.
There is no mandatory requirement that hart0 should always
come up. In fact, HiFive Unleashed SoC hart0 doesn't boot
in S-mode because it only has M-mode.
The timer driver should be bound for boot hart.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/cpu/riscv_cpu.c')
| -rw-r--r-- | drivers/cpu/riscv_cpu.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 5e15df5..f77c126 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -10,6 +10,8 @@ #include <dm/device-internal.h> #include <dm/lists.h> +DECLARE_GLOBAL_DATA_PTR; + static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) { const char *isa; @@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev) /* save the hart id */ plat->cpu_id = dev_read_addr(dev); - /* first examine the property in current cpu node */ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); /* if not found, then look at the parent /cpus node */ @@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev) &plat->timebase_freq); /* - * Bind riscv-timer driver on hart 0 + * Bind riscv-timer driver on boot hart. * * We only instantiate one timer device which is enough for U-Boot. * Pass the "timebase-frequency" value as the driver data for the @@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev) * Return value is not checked since it's possible that the timer * driver is not included. */ - if (!plat->cpu_id && plat->timebase_freq) { + if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) { drv = lists_driver_lookup_name("riscv_timer"); if (!drv) { debug("Cannot find the timer driver, not included?\n"); |