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| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:27:35 +0530 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-21 00:00:22 +0800 |
| commit | 09565686372c8113f67662bbe0376d90c5796a1b (patch) | |
| tree | e63a59f06e4b6150449cdc874b5e4ab5fc959aec /drivers/clk | |
| parent | ab0ce36a169dfc497733a530e15007e72ef286f5 (diff) | |
| download | u-boot-09565686372c8113f67662bbe0376d90c5796a1b.zip u-boot-09565686372c8113f67662bbe0376d90c5796a1b.tar.gz u-boot-09565686372c8113f67662bbe0376d90c5796a1b.tar.bz2 | |
clk: rockchip: rk3399: Set 50MHz ddr clock
Add support for setting 50MHz ddr clock.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 69a887f..2c00166 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ switch (set_rate) { + case 50 * MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2}; + break; case 200 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; |