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| author | Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> | 2024-03-11 21:33:45 +0000 |
|---|---|---|
| committer | Caleb Connolly <caleb.connolly@linaro.org> | 2024-04-04 17:46:45 +0200 |
| commit | 054eb8774309636263cbf1a9f5f67f8c8412619c (patch) | |
| tree | 2b0e4bf3dd852d814c59236e658485ed31c90ce1 /drivers/clk | |
| parent | 86eb5d834d220893b5dc262c5aea7f933e275a4f (diff) | |
| download | u-boot-054eb8774309636263cbf1a9f5f67f8c8412619c.zip u-boot-054eb8774309636263cbf1a9f5f67f8c8412619c.tar.gz u-boot-054eb8774309636263cbf1a9f5f67f8c8412619c.tar.bz2 | |
clk: qcom: clear div mask before assigning a new divider
The current behaviour does a bitwise OR of the previous and new
divider values, this is wrong as some bits may be set already. We
need to clear all the divider bits before applying new ones.
This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
[caleb: minor wording fix]
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/clock-qcom.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7c683e5..729d190 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -117,7 +117,8 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, /* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr); - cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); + cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | + CFG_SRC_DIV_MASK); cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ if (div) |