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| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-04-15 16:42:16 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-04-16 16:29:00 +0530 |
| commit | 33685372cf7dc8687c15e426b3a11281d4efce47 (patch) | |
| tree | 73626fad3bf7e55cb1f104be580a5a53a5c8326e /drivers/clk/sunxi | |
| parent | a93a55044bf777da701d7251e8b4a752b993a5b2 (diff) | |
| download | u-boot-33685372cf7dc8687c15e426b3a11281d4efce47.zip u-boot-33685372cf7dc8687c15e426b3a11281d4efce47.tar.gz u-boot-33685372cf7dc8687c15e426b3a11281d4efce47.tar.bz2 | |
clk: sunxi: r40: Fix GMAC reset reg offset
GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1: 68620c9698f109c1f001f80d282138a5c67cabef)
So, fix by updating the reg offset for RST_BUS_GMAC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/clk/sunxi')
| -rw-r--r-- | drivers/clk/sunxi/clk_r40.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 30beac9..44abc4f 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -62,7 +62,6 @@ static struct ccu_reset r40_resets[] = { [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), - [RST_BUS_GMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)), @@ -75,6 +74,8 @@ static struct ccu_reset r40_resets[] = { [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)), [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)), + [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), |