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| author | Alexander Kochetkov <al.kochet@gmail.com> | 2020-06-22 16:17:09 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2020-06-27 23:23:00 +0800 |
| commit | 5e15dcb4cbc7906690a759554be082b025d2aa52 (patch) | |
| tree | 062f046bb38297696549ee0e34650231e1e7b912 /drivers/clk/rockchip | |
| parent | a2b1cff8b86964ea630d23aa687c23bba40c9f4b (diff) | |
| download | u-boot-5e15dcb4cbc7906690a759554be082b025d2aa52.zip u-boot-5e15dcb4cbc7906690a759554be082b025d2aa52.tar.gz u-boot-5e15dcb4cbc7906690a759554be082b025d2aa52.tar.bz2 | |
rockchip: clk: rk3188: change APLL to safe 600MHz
The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock
driver") changed ARM clock from 600MHz to 1600MHz. It made boot
unstable due to the fact that PMIC at the start generates insufficient
voltage for operation. See also: commit f4f57c58b589 ("rockchip:
rk3188: Setup the armclk in spl").
Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock
driver").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3188.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 11e3bd3..aacc8cf 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -569,7 +569,8 @@ static int rk3188_clk_probe(struct udevice *dev) rkclk_init(priv->cru, priv->grf, priv->has_bwadj); /* Init CPU frequency */ - rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj); + rkclk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ, + priv->has_bwadj); #endif return 0; |