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| author | David Wu <david.wu@rock-chips.com> | 2017-09-20 14:28:19 +0800 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-10-01 00:33:29 +0200 |
| commit | ef4cf5ae393e4adf532f536d6da97c87f88db230 (patch) | |
| tree | 57fba8ac99e6c10b3ab505c6e8ded1637e850706 /drivers/clk/rockchip/clk_rk3328.c | |
| parent | 2e4ce50d1aca35d13944f48a7e15d0b63e86eb38 (diff) | |
| download | u-boot-ef4cf5ae393e4adf532f536d6da97c87f88db230.zip u-boot-ef4cf5ae393e4adf532f536d6da97c87f88db230.tar.gz u-boot-ef4cf5ae393e4adf532f536d6da97c87f88db230.tar.bz2 | |
rockchip: clk: Add SARADC clock support for rk3288
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers/clk/rockchip/clk_rk3328.c')
0 files changed, 0 insertions, 0 deletions