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| author | Kever Yang <kever.yang@rock-chips.com> | 2017-07-27 12:54:02 +0800 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-08-13 17:15:09 +0200 |
| commit | 217273cd441fe3d00a1bdad143dcb656854963f9 (patch) | |
| tree | 84b0975bed28db6f6f01bcf59d7d42cd23261e7d /drivers/clk/rockchip/clk_rk3036.c | |
| parent | 3a94d75d0e2a3b2519de51dfa1f369d976d9cccc (diff) | |
| download | u-boot-217273cd441fe3d00a1bdad143dcb656854963f9.zip u-boot-217273cd441fe3d00a1bdad143dcb656854963f9.tar.gz u-boot-217273cd441fe3d00a1bdad143dcb656854963f9.tar.bz2 | |
rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers/clk/rockchip/clk_rk3036.c')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3036.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 514ea88..83f4ae6 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -249,8 +249,9 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, /* mmc clock auto divide 2 in internal */ src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); - if (src_clk_div > 0x7f) { + if (src_clk_div > 128) { src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); + assert(src_clk_div - 1 < 128); mux = EMMC_SEL_24M; } else { mux = EMMC_SEL_GPLL; |