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| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | 2021-09-28 11:30:27 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-09-30 12:30:28 +0200 |
| commit | 1db1acbb848ef1b10eccedb52edd6c37078bbd38 (patch) | |
| tree | 73edeb47896e717c19fc707658574b2a43224e1f /drivers/clk/clk_versal.c | |
| parent | 0285d75a930f4b4d535b9d03972bdfa28e973083 (diff) | |
| download | u-boot-1db1acbb848ef1b10eccedb52edd6c37078bbd38.zip u-boot-1db1acbb848ef1b10eccedb52edd6c37078bbd38.tar.gz u-boot-1db1acbb848ef1b10eccedb52edd6c37078bbd38.tar.bz2 | |
clk: versal: Enable only GATE type clocks
Clocks should be enabled or disabled only if they are of GATE type
clocks. If they are not of GATE type clocks, don't touch them.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1632808827-6109-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/clk/clk_versal.c')
| -rw-r--r-- | drivers/clk/clk_versal.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 62523d2..a9dd57b 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk) clk_id = priv->clk[clk->id].clk_id; - return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + if (versal_clock_gate(clk_id)) + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + + return 0; } static struct clk_ops versal_clk_ops = { |