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| author | Simon Glass <sjg@chromium.org> | 2020-12-03 16:55:23 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2020-12-13 16:51:09 -0700 |
| commit | 8a8d24bdf174851ebb8607f359d54b72e3283b97 (patch) | |
| tree | 89fe2b9fd0c33209ce154170f9bda61f624dd9cd /drivers/clk/altera/clk-arria10.c | |
| parent | b012ff1f1b0d662587dcf8707fe7cbf1c1f35d2f (diff) | |
| download | u-boot-8a8d24bdf174851ebb8607f359d54b72e3283b97.zip u-boot-8a8d24bdf174851ebb8607f359d54b72e3283b97.tar.gz u-boot-8a8d24bdf174851ebb8607f359d54b72e3283b97.tar.bz2 | |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/clk/altera/clk-arria10.c')
| -rw-r--r-- | drivers/clk/altera/clk-arria10.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c index e1e4876..1812152 100644 --- a/drivers/clk/altera/clk-arria10.c +++ b/drivers/clk/altera/clk-arria10.c @@ -24,7 +24,7 @@ enum socfpga_a10_clk_type { SOCFPGA_A10_CLK_UNKNOWN_CLK, }; -struct socfpga_a10_clk_platdata { +struct socfpga_a10_clk_plat { enum socfpga_a10_clk_type type; struct clk_bulk clks; u32 regs; @@ -43,7 +43,7 @@ struct socfpga_a10_clk_platdata { static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev); u32 reg, maxval; if (plat->clks.count == 0) @@ -84,7 +84,7 @@ static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk) static int socfpga_a10_clk_endisable(struct clk *clk, bool enable) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev); struct clk *upclk = NULL; int ret; @@ -120,7 +120,7 @@ static int socfpga_a10_clk_disable(struct clk *clk) static ulong socfpga_a10_clk_get_rate(struct clk *clk) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev); struct clk *upclk = NULL; ulong rate = 0, reg, numer, denom; int ret; @@ -190,7 +190,7 @@ static struct clk_ops socfpga_a10_clk_ops = { */ static void socfpga_a10_handoff_workaround(struct udevice *dev) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(dev); const void *fdt = gd->fdt_blob; struct clk_bulk *bulk = &plat->clks; int i, ret, offset = dev_of_offset(dev); @@ -274,8 +274,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev) static int socfpga_a10_clk_probe(struct udevice *dev) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev); - struct socfpga_a10_clk_platdata *pplat; + struct socfpga_a10_clk_plat *plat = dev_get_plat(dev); + struct socfpga_a10_clk_plat *pplat; struct udevice *pdev; const void *fdt = gd->fdt_blob; int offset = dev_of_offset(dev); @@ -321,7 +321,7 @@ static int socfpga_a10_clk_probe(struct udevice *dev) static int socfpga_a10_of_to_plat(struct udevice *dev) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(dev); unsigned int divreg[3], gatereg[2]; int ret; @@ -359,5 +359,5 @@ U_BOOT_DRIVER(socfpga_a10_clk) = { .probe = socfpga_a10_clk_probe, .of_to_plat = socfpga_a10_of_to_plat, - .plat_auto = sizeof(struct socfpga_a10_clk_platdata), + .plat_auto = sizeof(struct socfpga_a10_clk_plat), }; |