Merge patch series "arm: Add Analog Devices SC5xx Machine Type"WIP/07May2024-next

Greg Malysa <greg.malysa@timesys.com> says:

This series adds support for the ADI SC5xx machine type and includes two
core drivers that are required for being able to boot any board--a UART
driver, the gptimer driver which is used as a clock reference (CNTVCNT
is not supported on the armv7 sc5xx SoCs) and the clock tree driver. Our
corresponding Linux support relies on u-boot configuring the clocks
correctly before booting, so it is not possible to boot any board
without the CGU/CDU configuration happening here. There are also no
board files, device trees, or defconfigs included here, but some common
definitions that will be used to build board files currently are. The
sc5xx SoCs themselves include many armv7 families (sc57x, sc58x, and
sc594) all using an ARM Cortex-A5, and one armv8 family (sc598) indended
to be a drop-in replacement for the SC594 in terms of peripherals, with
a Cortex-A55 instead.

Some of the configuration code in dmcinit and clkinit is quite scary and
causes a lot of checkpatch violations. It is modified from code
initially provided by ADI, but it has not been fully rewritten. There's
a question of how important it is to clean up this code--it has some
quality violations, but it has been in use (including in production) for
over two years and is known to work for performing the low level SoC
initialization, while a rewrite might introduce timing or sequence bugs
that could take a significant amount of time to detect in the future.

1 files changed, 48 insertions, 0 deletions

diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c
new file mode 100644
index 0000000..dcadcaf
--- /dev/null
+++ b/drivers/clk/adi/clk-shared.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include "clk.h"
+
+static ulong adi_get_rate(struct clk *clk)
+{
+	struct clk *c;
+	int ret;
+
+	ret = clk_get_by_id(clk->id, &c);
+	if (ret)
+		return ret;
+
+	return clk_get_rate(c);
+}
+
+static ulong adi_set_rate(struct clk *clk, ulong rate)
+{
+	//Not yet implemented
+	return 0;
+}
+
+static int adi_enable(struct clk *clk)
+{
+	//Not yet implemented
+	return 0;
+}
+
+static int adi_disable(struct clk *clk)
+{
+	//Not yet implemented
+	return 0;
+}
+
+const struct clk_ops adi_clk_ops = {
+	.set_rate = adi_set_rate,
+	.get_rate = adi_get_rate,
+	.enable = adi_enable,
+	.disable = adi_disable,
+};
+