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author | Tom Rini <trini@konsulko.com> | 2024-05-14 07:45:49 -0600 |
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committer | Tom Rini <trini@konsulko.com> | 2024-05-14 07:45:49 -0600 |
commit | 676903c1b97578a82c82a40293d4939cf687d9d9 (patch) | |
tree | 9a593aaa8cd82edb4c23146ebcfdc748e2e5a484 /drivers/cache | |
parent | d456f2fc54ebfa4215b310594b85b34d127c3b14 (diff) | |
parent | 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa (diff) | |
download | u-boot-676903c1b97578a82c82a40293d4939cf687d9d9.zip u-boot-676903c1b97578a82c82a40293d4939cf687d9d9.tar.gz u-boot-676903c1b97578a82c82a40293d4939cf687d9d9.tar.bz2 |
Merge https://source.denx.de/u-boot/custodians/u-boot-riscvWIP/14May2024
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20690
- RISC-V: Add NULL check after parsing compatible string
- Board: Add Milk-V Mars CM board
- Andes: Unify naming policy
Diffstat (limited to 'drivers/cache')
-rw-r--r-- | drivers/cache/Kconfig | 6 | ||||
-rw-r--r-- | drivers/cache/Makefile | 2 | ||||
-rw-r--r-- | drivers/cache/cache-andes-l2.c (renamed from drivers/cache/cache-v5l2.c) | 40 |
3 files changed, 24 insertions, 24 deletions
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 26c2d80..4f35865 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -22,11 +22,11 @@ config L2X0_CACHE ARMv7(32-bit) devices. The driver configures the cache settings found in the device tree. -config V5L2_CACHE - bool "Andes V5L2 cache driver" +config ANDES_L2_CACHE + bool "Andes L2 cache driver" select CACHE help - Support Andes V5L2 cache controller in AE350 platform. + Support Andes L2 cache controller in AE350 platform. It will configure tag and data ram timing control from the device tree and enable L2 cache. diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 78e673d..e1b71e0 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -3,6 +3,6 @@ obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_cache.o obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o -obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o +obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-andes-l2.c index f0b8ecc..7de8f16 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-andes-l2.c @@ -72,7 +72,7 @@ static u32 status_bit_offset = 0x4; DECLARE_GLOBAL_DATA_PTR; -struct v5l2_plat { +struct andes_l2_plat { struct l2cache *regs; u32 iprefetch; u32 dprefetch; @@ -80,9 +80,9 @@ struct v5l2_plat { u32 dram_ctl[2]; }; -static int v5l2_enable(struct udevice *dev) +static int andes_l2_enable(struct udevice *dev) { - struct v5l2_plat *plat = dev_get_plat(dev); + struct andes_l2_plat *plat = dev_get_plat(dev); volatile struct l2cache *regs = plat->regs; if (regs) @@ -91,9 +91,9 @@ static int v5l2_enable(struct udevice *dev) return 0; } -static int v5l2_disable(struct udevice *dev) +static int andes_l2_disable(struct udevice *dev) { - struct v5l2_plat *plat = dev_get_plat(dev); + struct andes_l2_plat *plat = dev_get_plat(dev); volatile struct l2cache *regs = plat->regs; u8 hart = gd->arch.boot_hart; void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart); @@ -113,9 +113,9 @@ static int v5l2_disable(struct udevice *dev) return 0; } -static int v5l2_of_to_plat(struct udevice *dev) +static int andes_l2_of_to_plat(struct udevice *dev) { - struct v5l2_plat *plat = dev_get_plat(dev); + struct andes_l2_plat *plat = dev_get_plat(dev); struct l2cache *regs; regs = dev_read_addr_ptr(dev); @@ -137,9 +137,9 @@ static int v5l2_of_to_plat(struct udevice *dev) return 0; } -static int v5l2_probe(struct udevice *dev) +static int andes_l2_probe(struct udevice *dev) { - struct v5l2_plat *plat = dev_get_plat(dev); + struct andes_l2_plat *plat = dev_get_plat(dev); struct l2cache *regs = plat->regs; u32 cfg_val, ctl_val; @@ -182,23 +182,23 @@ static int v5l2_probe(struct udevice *dev) return 0; } -static const struct udevice_id v5l2_cache_ids[] = { +static const struct udevice_id andes_l2_cache_ids[] = { { .compatible = "cache" }, {} }; -static const struct cache_ops v5l2_cache_ops = { - .enable = v5l2_enable, - .disable = v5l2_disable, +static const struct cache_ops andes_l2_cache_ops = { + .enable = andes_l2_enable, + .disable = andes_l2_disable, }; -U_BOOT_DRIVER(v5l2_cache) = { - .name = "v5l2_cache", +U_BOOT_DRIVER(andes_l2_cache) = { + .name = "andes_l2_cache", .id = UCLASS_CACHE, - .of_match = v5l2_cache_ids, - .of_to_plat = v5l2_of_to_plat, - .probe = v5l2_probe, - .plat_auto = sizeof(struct v5l2_plat), - .ops = &v5l2_cache_ops, + .of_match = andes_l2_cache_ids, + .of_to_plat = andes_l2_of_to_plat, + .probe = andes_l2_probe, + .plat_auto = sizeof(struct andes_l2_plat), + .ops = &andes_l2_cache_ops, .flags = DM_FLAG_PRE_RELOC, }; |