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authorDave Gerlach <d-gerlach@ti.com>2022-04-08 16:46:50 -0500
committerTom Rini <trini@konsulko.com>2022-04-20 11:14:39 -0400
commit270f7fd25b3d1e825d3364eee652c3ccc9d5aae4 (patch)
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parenta96d56572536f02c0d1f09f72bfedfa9cb4ae560 (diff)
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ram: k3-ddrss: Allow use of dt provided initial frequency
Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
index df3290a..1ea0a70 100644
--- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
+++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
@@ -39,6 +39,8 @@ Optional properties:
- reg: Must add "ss" to list if the above ss region is included.
- ti,ecc-enable: Boolean flag to enable ECC. This will reduce available DDR
by 1/9.
+- ti,ddr-freq0: Initial frequency set point, if not provided PLL bypass
+ frequency will be used.
Example (J721E):
================