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| author | Bin Meng <bmeng.cn@gmail.com> | 2017-05-31 01:04:15 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2017-06-05 08:55:22 +0800 |
| commit | f8f291b0962c795fcb025338d5c2284e2357a669 (patch) | |
| tree | 0cc3cea3163a8c0c35b0fecc67f99d2ea20e1007 /doc | |
| parent | 5e74e5a6826f8cf194ef5a569d6cafd2ed924f5c (diff) | |
| download | u-boot-f8f291b0962c795fcb025338d5c2284e2357a669.zip u-boot-f8f291b0962c795fcb025338d5c2284e2357a669.tar.gz u-boot-f8f291b0962c795fcb025338d5c2284e2357a669.tar.bz2 | |
x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer
At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/device-tree-bindings/misc/intel,baytrail-fsp.txt | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt index 691ae53..929ae88 100644 --- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -19,8 +19,6 @@ is matched up to Intel's E3800 FSPv4 release. - fsp,enable-sata - fsp,enable-azalia - fsp,enable-xhci -- fsp,enable-lpe -- fsp,lpss-sio-enable-pci-mode - fsp,enable-dma0 - fsp,enable-dma1 - fsp,enable-i2-c0 @@ -35,7 +33,6 @@ is matched up to Intel's E3800 FSPv4 release. - fsp,enable-hsi - fsp,mrc-debug-msg - fsp,isp-enable -- fsp,scc-enable-pci-mode - fsp,igd-render-standby - fsp,txe-uma-enable - fsp,emmc45-ddr50-enabled @@ -57,9 +54,12 @@ discovered by the FSP and used to setup main memory. - fsp,mrc-init-spd-addr2 - fsp,emmc-boot-mode - fsp,sata-mode +- fsp,lpe-mode +- fsp,lpss-sio-mode - fsp,igd-dvmt50-pre-alloc - fsp,aperture-size - fsp,gtt-size +- fsp,scc-mode - fsp,os-selection - fsp,emmc45-retune-timer-value @@ -110,8 +110,8 @@ Example (from MinnowMax Dual Core): fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = <SATA_MODE_AHCI>; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = <LPE_MODE_PCI>; + fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -126,7 +126,7 @@ Example (from MinnowMax Dual Core): fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>; fsp,aperture-size = <APERTURE_SIZE_256MB>; fsp,gtt-size = <GTT_SIZE_2MB>; - fsp,scc-enable-pci-mode; + fsp,scc-mode = <SCC_MODE_PCI>; fsp,os-selection = <OS_SELECTION_LINUX>; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; |