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author | Tom Rini <trini@konsulko.com> | 2021-04-20 07:32:04 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2021-04-20 07:32:04 -0400 |
commit | 842d049be23976ebcbb2522fa8d752d3aae8631a (patch) | |
tree | ca4ff1ffa3d447d51e945ce4cd9f75f6e80babe9 /doc | |
parent | eed05148c261e3b5f00b11a7a14bf0222b80a0ac (diff) | |
parent | 4e9bce12432492aa7a7c2121d9fae1640606ace5 (diff) | |
download | u-boot-WIP/20Apr2021.zip u-boot-WIP/20Apr2021.tar.gz u-boot-WIP/20Apr2021.tar.bz2 |
Merge branch '2021-04-20-assorted-improvements'WIP/20Apr2021
- ARM64 GIC fix, CONFIG_IRQ now moved to Kconfig
- IDE, lz4 fixes
- octeontx cleanups / enhancements
- highbank DM migration
- psci updates
- Enable use of -fstack-protector
Diffstat (limited to 'doc')
-rw-r--r-- | doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt | 45 | ||||
-rw-r--r-- | doc/usage/index.rst | 1 | ||||
-rw-r--r-- | doc/usage/reset.rst | 26 |
3 files changed, 72 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt b/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt new file mode 100644 index 0000000..2a60e49 --- /dev/null +++ b/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt @@ -0,0 +1,45 @@ +ANATOP REGULATOR + +Anatop is an integrated regulator inside i.MX6 SoC. + +Required properties: +- compatible: Must be "fsl,anatop-regulator". +- regulator-name: Name of the regulator +- anatop-reg-offset: u32 value representing the anatop MFD register offset. +- anatop-vol-bit-shift: u32 value representing the bit shift for the register. +- anatop-vol-bit-width: u32 value representing the number of bits used in the + register. +- anatop-min-bit-val: u32 value representing the minimum value of this + register. +- anatop-min-voltage: u32 value representing the minimum voltage of this + regulator. +- anatop-max-voltage: u32 value representing the maximum voltage of this + regulator. + +Optional properties: +- anatop-delay-reg-offset: u32 value representing the anatop MFD step time + register offset. +- anatop-delay-bit-shift: u32 value representing the bit shift for the step + time register. +- anatop-delay-bit-width: u32 value representing the number of bits used in + the step time register. +- anatop-enable-bit: u32 value representing regulator enable bit offset. +- vin-supply: input supply phandle. + +Example: + regulator-vddpu { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1300000>; + }; diff --git a/doc/usage/index.rst b/doc/usage/index.rst index b64cfe4..528b3c7 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -40,3 +40,4 @@ Shell commands sbi true scp03 + reset diff --git a/doc/usage/reset.rst b/doc/usage/reset.rst new file mode 100644 index 0000000..384d5d6 --- /dev/null +++ b/doc/usage/reset.rst @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +reset command +============= + +Synopsis +-------- + +:: + + reset [-w] + +Description +----------- + +Perform reset of the CPU. By default does COLD reset, which resets CPU, +DDR and peripherals, on some boards also resets external PMIC. + +-w + Do warm WARM, reset CPU but keep peripheral/DDR/PMIC active. + + +Return value +------------ + +The return value $? is always set to 0 (true). |