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authorJagan Teki <jteki@openedev.com>2015-08-15 23:06:56 +0530
committerJagan Teki <jteki@openedev.com>2015-10-25 20:17:01 +0530
commite5e7c747a0d591116f3418b071d2bb3629eafe56 (patch)
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parent70676cb3b503bea970eb4e1dd7ea902ec8ac2ea1 (diff)
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doc: device-tree-bindings: spi: Add zynq qspi info
Added device-tree-binding information for zynq qspi controller driver. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/spi/spi-zynq-qspi.txt26
1 files changed, 26 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/spi/spi-zynq-qspi.txt b/doc/device-tree-bindings/spi/spi-zynq-qspi.txt
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+++ b/doc/device-tree-bindings/spi/spi-zynq-qspi.txt
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+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible : Should be "xlnx,zynq-qspi-1.0".
+- reg : Physical base address and size of QSPI registers map.
+- interrupts : Property with a value describing the interrupt
+ number.
+- interrupt-parent : Must be core interrupt controller
+- clock-names : List of input clock names - "ref_clk", "pclk"
+ (See clock bindings for details).
+- clocks : Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs : Number of chip selects used.
+
+Example:
+ qspi@e000d000 {
+ compatible = "xlnx,zynq-qspi-1.0";
+ clock-names = "ref_clk", "pclk";
+ clocks = <&clkc 10>, <&clkc 43>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 19 4>;
+ num-cs = <1>;
+ reg = <0xe000d000 0x1000>;
+ } ;