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author | Andre Przywara <andre.przywara@arm.com> | 2023-10-18 01:06:52 +0100 |
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committer | Andre Przywara <andre.przywara@arm.com> | 2023-12-06 23:09:17 +0000 |
commit | d2e1cc69a24719e9939a84dc42bdf281af6ec35d (patch) | |
tree | 9cd1df143e22bacf1baa85d50e08e08a2f97a348 /configs | |
parent | 929f198d07f39b4a0b901a9f022581bf540bee1f (diff) | |
download | u-boot-d2e1cc69a24719e9939a84dc42bdf281af6ec35d.zip u-boot-d2e1cc69a24719e9939a84dc42bdf281af6ec35d.tar.gz u-boot-d2e1cc69a24719e9939a84dc42bdf281af6ec35d.tar.bz2 |
sunxi: H616: Add OrangePi Zero 3 board support
The OrangePi Zero 3 is a small development board featuring the Allwinner
H618 SoC, shipping with up to 4GB of DRAM, Gigabit Ethernet, a micro-HDMI
connector and two USB sockets.
The board uses LPDDR4 DRAM and an X-Powers AXP313a PMIC, support for
which was recently added to U-Boot.
Add a defconfig file selecting the right drivers and DRAM options.
Since the .dts file was synced from the Linux kernel repo already, we
just need to add one line to the Makefile to actually build the .dtb.
The DRAM parameters were derived from the values found in the BSP DRAM
drivers on the SPI NOR flash.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Tested-by: Bob McChesney <bob@electricworry.net>
Tested-by: Stephen Graf <stephen.graf@gmail.com>
Diffstat (limited to 'configs')
-rw-r--r-- | configs/orangepi_zero3_defconfig | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig new file mode 100644 index 0000000..5a019fe --- /dev/null +++ b/configs/orangepi_zero3_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e +CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee +CONFIG_DRAM_SUN50I_H616_TPR6=0x44000000 +CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 +CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624 +CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_CLK=792 +CONFIG_USB1_VBUS_PIN="PC16" +CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP313_POWER=y +CONFIG_SPI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y |