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| author | Marek Vasut <marex@denx.de> | 2023-12-07 18:50:32 +0100 |
|---|---|---|
| committer | Fabio Estevam <festevam@denx.de> | 2023-12-14 15:29:08 -0300 |
| commit | cfdbdf78428bdb1e91c39b8916627fbc22ea2540 (patch) | |
| tree | 07b55c753480f8a08f1a7a533b66e893eb76aae9 /configs | |
| parent | c4cc14433dcdb9480eb496541dc7960f7eb718c0 (diff) | |
| download | u-boot-cfdbdf78428bdb1e91c39b8916627fbc22ea2540.zip u-boot-cfdbdf78428bdb1e91c39b8916627fbc22ea2540.tar.gz u-boot-cfdbdf78428bdb1e91c39b8916627fbc22ea2540.tar.bz2 | |
ARM: imx: Update DRAM timings with inline ECC on Data Modul i.MX8M Plus eDM SBC
Import DRAM timings generated by the DDR tool 3.31 which introduce assorted
tweaks to the DRAM controller settings. Furthermore, enable DBI to improve
noise resilience of the DRAM bus by reducing the number of bit changes on
the bus.
Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors
reported by EDAC . It is not entirely clear why the slightly faster setting
does produce sporadic correctable errors, while this one does not, but this
could be related to simpler PLL setting at 3600 MTps.
Enable inline ECC which is necessary to detect ECC errors and collect
statistics by the EDAC driver in Linux. This reduces the DRAM size by
64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available
DRAM size becomes 3.5 GiB .
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/imx8mp_data_modul_edm_sbc_defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index 30f8636..3974e37 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -165,6 +165,7 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y CONFIG_FSL_CAAM=y +CONFIG_IMX8M_DRAM_INLINE_ECC=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y |