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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2019-10-11 13:28:19 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-10-25 00:48:32 +0530 |
| commit | 8651593a8ce0c0599c993d76d2a927b125175cef (patch) | |
| tree | 44f33fa7505061b547d8ee317dd673b9ec691509 /configs/socfpga_arria5_defconfig | |
| parent | d66e07cdf9ab6f84ce121009b08860261bca7df2 (diff) | |
| download | u-boot-8651593a8ce0c0599c993d76d2a927b125175cef.zip u-boot-8651593a8ce0c0599c993d76d2a927b125175cef.tar.gz u-boot-8651593a8ce0c0599c993d76d2a927b125175cef.tar.bz2 | |
spi-nor: spi-nor-ids: Add entries for mt25q variants
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries
for the same. These flashes have bit 6 set in 5th byte of READ ID
response when compared to n25q* variants.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'configs/socfpga_arria5_defconfig')
0 files changed, 0 insertions, 0 deletions