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| author | Marek Vasut <marex@denx.de> | 2022-06-13 14:35:25 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-06-15 11:34:38 +0200 |
| commit | 1a558fafbbdff80cb6a7c8e883addec7f02fe8e5 (patch) | |
| tree | bbe5303c7e153389b9f6e9ac68b6abc3be7a90cc /configs/P2020RDB-PC_SPIFLASH_defconfig | |
| parent | 66e54716cfd1be2ca3a2a17749b45b7e3980f050 (diff) | |
| download | u-boot-1a558fafbbdff80cb6a7c8e883addec7f02fe8e5.zip u-boot-1a558fafbbdff80cb6a7c8e883addec7f02fe8e5.tar.gz u-boot-1a558fafbbdff80cb6a7c8e883addec7f02fe8e5.tar.bz2 | |
spi: nxp_fspi: Fix clock imbalance
The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(),
where the IP clock are initially disabled. Drop the second disabling of
clock to prevent clock enable/disable imbalance reported by clock core:
"
clk qspi_root_clk already disabled
"
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'configs/P2020RDB-PC_SPIFLASH_defconfig')
0 files changed, 0 insertions, 0 deletions