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authorHaibo Chen <haibo.chen@nxp.com>2020-06-22 19:38:04 +0800
committerPeng Fan <peng.fan@nxp.com>2020-06-24 14:05:30 +0800
commitba61676ff9f8225ebc0ea33ad9f48862e718fd01 (patch)
tree3e85f5ccf2d78659bbb239d0ee9caa4cf6d8556f /cmd
parent135c10a7834aa7e0f26f52e5173925e695cba48f (diff)
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mmc: fsl_esdhc_imx: disable the CMD CRC check for standard tuning
In current code, we add 1ms dealy after each tuning command for standard tuning method. Adding this 1ms dealy is because USDHC default check the CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning IC logic do not wait for the tuning data sending out by the card, trigger the buffer read ready interrupt immediately, and step to next cycle. So when next time the new tuning command send out by USDHC, card may still not send out the tuning data of the upper command,then some eMMC cards may stuck, can't response to any command, block the whole tuning procedure. If do not check the CMD CRC for tuning, then do not has this issue. USDHC will wait for the tuning data of each tuning command and check them. If the tuning data pass the check, it also means the CMD line also okay for tuning. So this patch disable the CMD CRC check for tuning, save some time for the whole tuning procedure. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'cmd')
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