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authorTom Rini <trini@konsulko.com>2021-09-29 07:58:20 -0400
committerTom Rini <trini@konsulko.com>2021-09-29 07:58:20 -0400
commit6eecaf5d0f6b9a500dd5798f1f2bc8296bcfe158 (patch)
tree1307de30a7d4cc6e5db9a3d78f583d288a5dbbdb /board
parentba17871884c10f64082ddba2f0632ec44a3ae490 (diff)
parent4df9f5e39fb224a4857c3411b4cbe419e4d339e8 (diff)
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u-boot-6eecaf5d0f6b9a500dd5798f1f2bc8296bcfe158.tar.gz
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Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net into nextWIP/29Sep2021-next
- Fix some non-NULL terminated strings in the networking subsystem - net: tsec: Mark tsec_get_interface as __maybe_unused
Diffstat (limited to 'board')
-rw-r--r--board/Marvell/octeon_ebb7304/board.c6
-rw-r--r--board/freescale/ls1012aqds/eth.c4
-rw-r--r--board/freescale/ls1012aqds/ls1012aqds.c4
-rw-r--r--board/freescale/ls1012aqds/ls1012aqds_pfe.h2
-rw-r--r--board/freescale/ls1012ardb/eth.c4
-rw-r--r--board/freescale/ls1021atsn/ls1021atsn.c2
-rw-r--r--board/freescale/ls1043aqds/README2
-rw-r--r--board/freescale/ls1043aqds/eth.c12
-rw-r--r--board/freescale/ls1043ardb/README2
-rw-r--r--board/freescale/ls1043ardb/eth.c2
-rw-r--r--board/freescale/ls1046aqds/README2
-rw-r--r--board/freescale/ls1046aqds/eth.c8
-rw-r--r--board/freescale/ls1046ardb/README4
-rw-r--r--board/freescale/ls1046ardb/eth.c2
-rw-r--r--board/freescale/ls1088a/README4
-rw-r--r--board/freescale/ls1088a/eth_ls1088ardb.c6
-rw-r--r--board/freescale/ls2080aqds/README2
-rw-r--r--board/freescale/ls2080aqds/eth.c13
-rw-r--r--board/freescale/ls2080ardb/README2
-rw-r--r--board/freescale/t102xrdb/README2
-rw-r--r--board/freescale/t102xrdb/eth_t102xrdb.c8
-rwxr-xr-xboard/freescale/t208xqds/README18
-rw-r--r--board/freescale/t208xqds/eth_t208xqds.c22
-rw-r--r--board/freescale/t208xqds/t208xqds.c8
-rw-r--r--board/freescale/t208xrdb/README4
-rw-r--r--board/freescale/t4rdb/eth.c2
-rw-r--r--board/gdsys/a38x/ihs_phys.c4
27 files changed, 74 insertions, 77 deletions
diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c
index 9aac5f0..e8e2d54 100644
--- a/board/Marvell/octeon_ebb7304/board.c
+++ b/board/Marvell/octeon_ebb7304/board.c
@@ -339,7 +339,7 @@ void __fixup_fdt(void)
case CVMX_QLM_MODE_XFI:
case CVMX_QLM_MODE_RGMII_XFI:
case CVMX_QLM_MODE_RGMII_XFI_1X1:
- type_str = "xfi";
+ type_str = "10gbase-r";
break;
case CVMX_QLM_MODE_10G_KR:
case CVMX_QLM_MODE_RGMII_10G_KR:
@@ -393,7 +393,7 @@ void __fixup_fdt(void)
if (pmd_control.s.train_en)
type_str = "10G_KR";
else
- type_str = "xfi";
+ type_str = "10gbase-r";
break;
case 4:
if (pmd_control.s.train_en)
@@ -618,7 +618,7 @@ static void board_configure_qlms(void)
speed[qlm] = 103125;
}
printf("QLM %d: XLAUI\n", qlm);
- } else if (!strncmp(mode_str, "xfi", 3)) {
+ } else if (!strncmp(mode_str, "10gbase-r", 3)) {
bool rgmii = false;
speed[qlm] = 103125;
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
index 8189f41..27f69ab 100644
--- a/board/freescale/ls1012aqds/eth.c
+++ b/board/freescale/ls1012aqds/eth.c
@@ -244,7 +244,7 @@ int pfe_eth_board_init(struct udevice *dev)
bus = miiphy_get_dev_by_name(mdio_name);
pfe_set_mdio(1, bus);
pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
data8 = QIXIS_READ(brdcfg[12]);
data8 |= 0x20;
@@ -263,7 +263,7 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_mdio(0, bus);
pfe_set_phy_address_mode(0,
CONFIG_PFE_SGMII_2500_PHY1_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
}
break;
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 33a0910..6e21040 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -265,7 +265,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
ETH_1_2_5G_MDIO_MUX);
prop_val.phy_mask = cpu_to_fdt32(
ETH_2_5G_MDIO_PHY_MASK);
- prop_val.phy_mode = "sgmii-2500";
+ prop_val.phy_mode = "2500base-x";
pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
ETH_1_MDIO);
} else {
@@ -277,7 +277,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
ETH_2_2_5G_MDIO_MUX);
prop_val.phy_mask = cpu_to_fdt32(
ETH_2_5G_MDIO_PHY_MASK);
- prop_val.phy_mode = "sgmii-2500";
+ prop_val.phy_mode = "2500base-x";
pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
ETH_2_MDIO);
}
diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
index 05ccb71..5ab283c 100644
--- a/board/freescale/ls1012aqds/ls1012aqds_pfe.h
+++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
@@ -17,7 +17,7 @@
#define ETH_1_2_5G_PHY_ID 0x1
#define ETH_1_2_5G_MDIO_MUX 0x2
#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
-#define ETH_2_5G_PHY_MODE "sgmii-2500"
+#define ETH_2_5G_PHY_MODE "2500base-x"
#define ETH_2_2_5G_BUS_ID 0x1
#define ETH_2_2_5G_PHY_ID 0x2
#define ETH_2_2_5G_MDIO_MUX 0x3
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index bb3fbc7..565f800 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -121,12 +121,12 @@ int pfe_eth_board_init(struct udevice *dev)
/* MAC1 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC1_PHY_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
} else {
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
}
break;
default:
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index c1acd30..f31e16c 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP Semiconductors
+/* Copyright 2016-2019 NXP
*/
#include <common.h>
#include <clock_legacy.h>
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
index 913537d..f5aa51d 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -18,7 +18,7 @@ SoC overview.
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
-IFC/Local Bus
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index c3efe8a..e156ba0 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -176,7 +176,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
"sgmii-riser-s4-p1");
}
} else if (fm_info_get_enet_if(port) ==
- PHY_INTERFACE_MODE_SGMII_2500) {
+ PHY_INTERFACE_MODE_2500BASEX) {
/* 2.5G SGMII interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
@@ -187,7 +187,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (mdio_mux[port]) {
case EMI1_SLOT1:
@@ -242,13 +242,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
"qsgmii");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
port == FM1_10GEC1) {
- /* XFI interface */
+ /* 10GBase-R interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
f_link.link_speed = cpu_to_fdt32(10000);
f_link.pause = 0;
f_link.asym_pause = 0;
- /* no PHY for XFI */
+ /* no PHY for 10GBase-R */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
@@ -430,12 +430,12 @@ int board_eth_init(struct bd_info *bis)
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
- } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ } else if (interface == PHY_INTERFACE_MODE_2500BASEX) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
index 709ddbb..66ee578 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -17,7 +17,7 @@ SoC overview.
- PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
standard PCIe card
- QSGMII with x4 RJ45 connector
- - XFI with x1 RJ45 connector
+ - 10GBase-R with x1 RJ45 connector
- DDR Controller
- 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
-IFC/Local Bus
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
index 1f01c15..fa59116 100644
--- a/board/freescale/ls1043ardb/eth.c
+++ b/board/freescale/ls1043ardb/eth.c
@@ -65,7 +65,7 @@ int board_eth_init(struct bd_info *bis)
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
- /* XFI on lane A, MAC 9 */
+ /* 10GBase-R on lane A, MAC 9 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(FM1_10GEC1, dev);
diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README
index b8fa326..d646901 100644
--- a/board/freescale/ls1046aqds/README
+++ b/board/freescale/ls1046aqds/README
@@ -18,7 +18,7 @@ SoC overview.
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
-IFC/Local Bus
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index 33db552..8233f54 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c
@@ -178,7 +178,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
default:
break;
}
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) {
/* 2.5G SGMII interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
@@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
@@ -217,13 +217,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
/* Backplane KR mode: skip fixups */
printf("Interface %d in backplane KR mode\n", port);
} else {
- /* XFI interface */
+ /* 10GBase-R interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
f_link.link_speed = cpu_to_fdt32(10000);
f_link.pause = 0;
f_link.asym_pause = 0;
- /* no PHY for XFI */
+ /* no PHY for 10GBase-R */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link,
sizeof(f_link));
diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
index a38c9d4..1660f7c 100644
--- a/board/freescale/ls1046ardb/README
+++ b/board/freescale/ls1046ardb/README
@@ -14,8 +14,8 @@ SoC overview.
LS1046ARDB board Overview
-----------------------
- SERDES1 Connections, 4 lanes supporting:
- - Lane0: XFI with x1 RJ45 connector
- - Lane1: XFI Cage
+ - Lane0: 10GBase-R with x1 RJ45 connector
+ - Lane1: 10GBase-R Cage
- Lane2: SGMII.5
- Lane3: SGMII.6
- SERDES2 Connections, 4 lanes supporting:
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
index 4905302..a3e147a 100644
--- a/board/freescale/ls1046ardb/eth.c
+++ b/board/freescale/ls1046ardb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(struct bd_info *bis)
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
- /* XFI on lane A, MAC 9 */
+ /* 10GBase-R on lane A, MAC 9 */
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(FM1_10GEC1, dev);
diff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README
index aa0fb6a..5315909 100644
--- a/board/freescale/ls1088a/README
+++ b/board/freescale/ls1088a/README
@@ -42,7 +42,7 @@ Alternately you can use this command to switch from QSPI to SD
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - XFI
+ - 10GBase-R
- QSGMII
- DDR Controller
- One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
@@ -106,7 +106,7 @@ SW12 1111 1111
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - 2 XFI
+ - 2 10GBase-R
- QSGMII, SGMII with help for Riser card
- 2 RGMII
- 5 slot for Riser card or PCIe NIC
diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
index a8e9ef1..1ba5e94 100644
--- a/board/freescale/ls1088a/eth_ls1088ardb.c
+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -52,9 +52,9 @@ int board_eth_init(struct bd_info *bis)
switch (srds_s1) {
case 0x1D:
/*
- * XFI does not need a PHY to work, but to avoid U-boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
+ * 10GBase-R does not need a PHY to work, but to avoid U-boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
* MAC error.
*/
wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 8e31e9e..04c1941 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -19,7 +19,7 @@ LS2088A SoC overview.
- QSGMII
- SATA 3.0
- XAUI
- - XFI
+ - 10GBase-R
- DDR Controller
- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
chip-selects and two DIMM connectors. Support is up to 2133MT/s.
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 914cd0a..7db3789 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -874,13 +874,12 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
case 0x4B:
case 0x4C:
/*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
- * MAC, and should not use a real XAUI PHY address, since
- * MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the XFI MAC, which will cause
- * error.
+ * 10GBase-R does not need a PHY to work, but to avoid U-Boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
+ * MAC, and should not use a real XAUI PHY address, since MDIO
+ * can access it successfully, and then MDIO thinks the XAUI
+ * card is used for the 10GBase-R MAC, which will cause error.
*/
wriop_set_phy_address(i, 0, i + 4);
ls2080a_qds_enable_SFP_TX(SFP_TX);
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 205c45c..75a633c 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -18,7 +18,7 @@ LS2081A, LS2088A SoC overview.
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
chip-selects and two DIMM connectors. Support is up to 2133MT/s.
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
index dde3f8c..84deb95 100644
--- a/board/freescale/t102xrdb/README
+++ b/board/freescale/t102xrdb/README
@@ -39,7 +39,7 @@ The T1024 SoC includes the following function and features:
- One QSGMII interface
- Four SGMII interface supporting 1000 Mbps
- Three SGMII interfaces supporting up to 2500 Mbps
- - 10GbE XFI or 10Base-KR interface
+ - 10GBase-R or 10Base-KR interface
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 56e6109..4f04d2e 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis)
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
- /* set 10G XFI with Aquantia AQR105 PHY */
+ /* set 10GBase-R with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
#endif
@@ -103,7 +103,7 @@ int board_eth_init(struct bd_info *bis)
#endif
fm_info_set_mdio(i, dev);
break;
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
@@ -133,12 +133,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
#if defined(CONFIG_TARGET_T1024RDB)
- if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+ if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
(port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
#endif
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
index d690857..b52d961 100755
--- a/board/freescale/t208xqds/README
+++ b/board/freescale/t208xqds/README
@@ -55,14 +55,14 @@ Memory:
- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- - Four 10Gbps XFI on-board cages
+ - Four 10GBase-R on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
+ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
@@ -85,14 +85,14 @@ System Logic:
- QIXIS-II FPGA system controll
Debug Features:
- Support Legacy, COP/JTAG, Aurora, Event and EVT
-XFI:
- - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+10GBase-R:
+ - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
a on-board SFP+ cages, which to house optical module (fiber cable) or
direct attach cable(copper), the copper cable is used to emulate
10GBASE-KR scenario.
- So, for XFI usage, there are two scenarios, one will use fiber cable,
+ So, for 10GBase-R usage, there are two scenarios, one will use fiber cable,
another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-Boot
+ introduced to indicate a 10GBase-R port will use copper cable, and U-Boot
will fixup the dtb accordingly.
It's used as: fsl_10gkr_copper:<10g_mac_name>
The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
@@ -100,10 +100,10 @@ XFI:
"fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
will be used by default.
for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
- hwconfig, then both four XFI ports will use copper cable.
+ hwconfig, then both four 10GBase-R ports will use copper cable.
set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
- XFI ports will use copper cable, the other two XFI ports will use fiber
- cable.
+ 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use
+ fiber cable.
1000BASE-KX(1G-KX):
- T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 705387a..2d7fc8b 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -310,16 +310,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
switch (srds_s1) {
- case 0x66: /* XFI interface */
+ case 0x66: /* 10GBase-R interface */
case 0x6b:
case 0x6c:
case 0x6d:
case 0x71:
/*
- * if the 10G is XFI, check hwconfig to see what is the
- * media type, there are two types, fiber or copper,
- * fix the dtb accordingly.
- */
+ * Check hwconfig to see what is the media type, there
+ * are two types, fiber or copper, fix the dtb
+ * accordingly.
+ */
switch (port) {
case FM1_10GEC1:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
@@ -378,7 +378,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
printf("Interface %d in backplane KR mode\n",
port);
} else {
- /* fixed-link for XFI fiber cable */
+ /* fixed-link for 10GBase-R fiber cable */
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
@@ -538,12 +538,12 @@ int board_eth_init(struct bd_info *bis)
case 0x66:
case 0x67:
/*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
+ * 10GBase-R does not need a PHY to work, but to avoid U-Boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
* MAC, and should not use a real XAUI PHY address, since
* MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the XFI MAC, which will cause
+ * the XAUI card is used for the 10GBase-R MAC, which will cause
* error.
*/
fm_info_set_phy_address(FM1_10GEC1, 4);
@@ -701,7 +701,7 @@ int board_eth_init(struct bd_info *bis)
(srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
(srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
(srds_s1 == 0x71)) {
- /* As XFI is in cage intead of a slot, so
+ /* As 10GBase-R is in cage intead of a slot, so
* ensure doesn't disable the corresponding port
*/
break;
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 715de10..e54672a 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -136,14 +136,14 @@ int brd_mux_lane_to_slot(void)
break;
case 0x66:
case 0x67:
- /* SD1(A:D) => XFI cage
+ /* SD1(A:D) => 10GBase-R cage
* SD1(E:H) => SLOT1 PCIe4
*/
QIXIS_WRITE(brdcfg[12], 0xfe);
break;
case 0x6a:
case 0x6b:
- /* SD1(A:D) => XFI cage
+ /* SD1(A:D) => 10GBase-R cage
* SD1(E) => SLOT1 PCIe4
* SD1(F:H) => SLOT2 SGMII
*/
@@ -151,14 +151,14 @@ int brd_mux_lane_to_slot(void)
break;
case 0x6c:
case 0x6d:
- /* SD1(A:B) => XFI cage
+ /* SD1(A:B) => 10GBase-R cage
* SD1(C:D) => SLOT3 SGMII
* SD1(E:H) => SLOT1 PCIe4
*/
QIXIS_WRITE(brdcfg[12], 0xda);
break;
case 0x6e:
- /* SD1(A:B) => SFP Module, XFI
+ /* SD1(A:B) => SFP Module, 10GBase-R
* SD1(C:D) => SLOT3 SGMII
* SD1(E:F) => SLOT1 PCIe4 x2
* SD1(G:H) => SLOT2 SGMII
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
index ec47c96..c4bfd3b 100644
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@@ -54,7 +54,7 @@ Differences between T2080 and T2081
T2080PCIe-RDB board Overview
----------------------------
- SERDES Configuration
- - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+ - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
@@ -62,7 +62,7 @@ T2080PCIe-RDB board Overview
- SerDes-2 Lane G-H: to SATA1 & SATA2
- Ethernet
- Two on-board 10M/100M/1G RGMII ethernet ports
- - Two on-board 10Gbps XFI fiber ports
+ - Two on-board 10GBase-R fiber ports
- Two on-board 10Gbps Base-T copper ports
- DDR Memory
- Supports 72bit 4GB DDR3-LP SODIMM
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index c815a3a..34ffaa6 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -106,7 +106,7 @@ int board_eth_init(struct bd_info *bis)
#if (CONFIG_SYS_NUM_FMAN == 2)
if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
- /* SGMII && XFI */
+ /* SGMII && 10GBase-R */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c
index c23d150..e09c000 100644
--- a/board/gdsys/a38x/ihs_phys.c
+++ b/board/gdsys/a38x/ihs_phys.c
@@ -110,9 +110,7 @@ int register_miiphy_bus(uint k, struct mii_dev **bus)
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name,
- name,
- MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;