Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
  fsl-layerscape, pci, icid, PSCI

11 files changed, 17 insertions, 9 deletions

diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 8b89c10..1b1fd69 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -1,5 +1,5 @@
 config CHAIN_OF_TRUST
-	depends on !FIT_SIGNATURE && SECURE_BOOT
+	depends on !FIT_SIGNATURE && NXP_ESBC
 	imply CMD_BLOB
 	imply CMD_HASH if ARM
 	select FSL_CAAM
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index a9d61a8..b0e109f 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -75,7 +75,7 @@ obj-$(CONFIG_TARGET_P5040DS)	+= p_corenet/
 
 obj-$(CONFIG_LAYERSCAPE_NS_ACCESS)	+= ns_access.o
 
-ifdef CONFIG_SECURE_BOOT
+ifdef CONFIG_NXP_ESBC
 obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
 endif
 obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 3d9459b..c0ab1a5 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -43,7 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* *I*** - Covers boot page */
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
 
-#if !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_NXP_ESBC)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index fbd9a26..9bc78d6 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -196,7 +196,7 @@ int board_init(void)
 	init_final_memctl_regs();
 #endif
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 	/* In case of Secure Boot, the IBR configures the SMMU
 	 * to allow only Secure transactions.
 	 * SMMU must be reset in bypass mode.
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index 41412a7..ac2f8ee 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -126,7 +126,7 @@ int checkboard(void)
 
 int board_init(void)
 {
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 	/*
 	 * In case of Secure Boot, the IBR configures the SMMU
 	 * to allow only Secure transactions.
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index b71c174..6a51dcd 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -407,7 +407,7 @@ int board_init(void)
 	ppa_init();
 #endif
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 	/*
 	 * In case of Secure Boot, the IBR configures the SMMU
 	 * to allow only Secure transactions.
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 0a73fe8..cc6bd88 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -69,7 +69,7 @@ int board_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 	/*
 	 * In case of Secure Boot, the IBR configures the SMMU
 	 * to allow only Secure transactions.
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 91c8035..25e80c8 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -20,6 +20,7 @@
 #include <hwconfig.h>
 #include <fsl_sec.h>
 #include <asm/arch/ppa.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 
 
 #include "../common/qixis.h"
@@ -358,6 +359,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_board_enet(blob);
 #endif
 
+	fdt_fixup_icid(blob);
+
 	return 0;
 }
 #endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index e20267f..6a1b8e3 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -22,6 +22,7 @@
 #include <asm/arch/soc.h>
 #include <asm/arch/ppa.h>
 #include <fsl_sec.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 
 #ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
@@ -478,6 +479,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_board_enet(blob);
 #endif
 
+	fdt_fixup_icid(blob);
+
 	return 0;
 }
 #endif
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index b509c03..eff1274 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -27,6 +27,7 @@
 #include "../common/qixis.h"
 #include "../common/vid.h"
 #include <fsl_immap.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 
 #ifdef CONFIG_EMC2305
 #include "../common/emc2305.h"
@@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fsl_mc_fixup_iommu_map_entry(blob);
 	fdt_fixup_board_enet(blob);
 #endif
+	fdt_fixup_icid(blob);
 
 	return 0;
 }
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 6511c04..9dcba79 100644
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -28,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
-	!defined(CONFIG_SECURE_BOOT)
+	!defined(CONFIG_NXP_ESBC)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
 	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
@@ -37,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
 
-#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
+#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
 	 * the physical address of the SRAM is at 0xbffc0000,