Merge tag 'next-20220328' of https://source.denx.de/u-boot/custodians/u-boot-video into nextWIP/28Mar2022

 - drop old CFB code
 - drop CONFIG_LCD_BMP_RLE8

26 files changed, 0 insertions, 1364 deletions

diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index f13fa11..19af596 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -39,7 +39,6 @@
 #include <power/regulator.h>
 #include <power/da9063_pmic.h>
 #include <splash.h>
-#include <video_fb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 0ddfb59..f13965d 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -44,16 +44,12 @@ ifndef CONFIG_RAMBOOT_PBL
 obj-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
 endif
 
-obj-$(CONFIG_FSL_DIU_CH7301)	+= diu_ch7301.o
-
 ifdef CONFIG_ARM
 obj-$(CONFIG_DEEP_SLEEP)		+= arm_sleep.o
 else
 obj-$(CONFIG_DEEP_SLEEP)		+= mpc85xx_sleep.o
 endif
 
-obj-$(CONFIG_FSL_DCU_SII9022A)    += dcu_sii9022a.o
-
 obj-$(CONFIG_TARGET_MPC8548CDS)	+= cds_pci_ft.o
 
 obj-$(CONFIG_TARGET_MPC8536DS)	+= ics307_clk.o
diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c
deleted file mode 100644
index 9137d24..0000000
--- a/board/freescale/common/dcu_sii9022a.c
+++ /dev/null
@@ -1,248 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <fsl_dcu_fb.h>
-#include <i2c.h>
-#include <linux/fb.h>
-
-#define PIXEL_CLK_LSB_REG		0x00
-#define PIXEL_CLK_MSB_REG		0x01
-#define VERT_FREQ_LSB_REG		0x02
-#define VERT_FREQ_MSB_REG		0x03
-#define TOTAL_PIXELS_LSB_REG		0x04
-#define TOTAL_PIXELS_MSB_REG		0x05
-#define TOTAL_LINES_LSB_REG		0x06
-#define TOTAL_LINES_MSB_REG		0x07
-#define TPI_INBUS_FMT_REG		0x08
-#define TPI_INPUT_FMT_REG		0x09
-#define TPI_OUTPUT_FMT_REG		0x0A
-#define TPI_SYS_CTRL_REG		0x1A
-#define TPI_PWR_STAT_REG		0x1E
-#define TPI_AUDIO_HANDING_REG		0x25
-#define TPI_AUDIO_INTF_REG		0x26
-#define TPI_AUDIO_FREQ_REG		0x27
-#define TPI_SET_PAGE_REG		0xBC
-#define TPI_SET_OFFSET_REG		0xBD
-#define TPI_RW_ACCESS_REG		0xBE
-#define TPI_TRANS_MODE_REG		0xC7
-
-#define TPI_INBUS_CLOCK_RATIO_1		(1 << 6)
-#define TPI_INBUS_FULL_PIXEL_WIDE	(1 << 5)
-#define TPI_INBUS_RISING_EDGE		(1 << 4)
-#define TPI_INPUT_CLR_DEPTH_8BIT	(0 << 6)
-#define TPI_INPUT_VRANGE_EXPAN_AUTO	(0 << 2)
-#define TPI_INPUT_CLR_RGB		(0 << 0)
-#define TPI_OUTPUT_CLR_DEPTH_8BIT	(0 << 6)
-#define TPI_OUTPUT_VRANGE_COMPRE_AUTO	(0 << 2)
-#define TPI_OUTPUT_CLR_HDMI_RGB		(0 << 0)
-#define TPI_SYS_TMDS_OUTPUT		(0 << 4)
-#define TPI_SYS_AV_NORAML		(0 << 3)
-#define TPI_SYS_AV_MUTE			(1 << 3)
-#define TPI_SYS_DVI_MODE		(0 << 0)
-#define TPI_SYS_HDMI_MODE		(1 << 0)
-#define TPI_PWR_STAT_MASK		(3 << 0)
-#define TPI_PWR_STAT_D0			(0 << 0)
-#define TPI_AUDIO_PASS_BASIC		(0 << 0)
-#define TPI_AUDIO_INTF_I2S		(2 << 6)
-#define TPI_AUDIO_INTF_NORMAL		(0 << 4)
-#define TPI_AUDIO_TYPE_PCM		(1 << 0)
-#define TPI_AUDIO_SAMP_SIZE_16BIT	(1 << 6)
-#define TPI_AUDIO_SAMP_FREQ_44K		(2 << 3)
-#define TPI_SET_PAGE_SII9022A		0x01
-#define TPI_SET_OFFSET_SII9022A		0x82
-#define TPI_RW_EN_SRC_TERMIN		(1 << 0)
-#define TPI_TRANS_MODE_ENABLE		(0 << 7)
-
-/* Programming of Silicon SIi9022a HDMI Transmitter */
-int dcu_set_dvi_encoder(struct fb_videomode *videomode)
-{
-	u8 temp;
-	u16 temp1, temp2;
-	u32 temp3;
-#if CONFIG_IS_ENABLED(DM_I2C)
-	struct udevice *dev;
-	int ret;
-
-	ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
-				      CONFIG_SYS_I2C_DVI_ADDR,
-				      1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       CONFIG_SYS_I2C_DVI_BUS_NUM);
-		return ret;
-	}
-
-	/* Enable TPI transmitter mode */
-	temp = TPI_TRANS_MODE_ENABLE;
-	dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1);
-
-	/* Enter into D0 state, full operation */
-	dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1);
-	temp &= ~TPI_PWR_STAT_MASK;
-	temp |= TPI_PWR_STAT_D0;
-	dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1);
-
-	/* Enable source termination */
-	temp = TPI_SET_PAGE_SII9022A;
-	dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1);
-	temp = TPI_SET_OFFSET_SII9022A;
-	dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1);
-
-	dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1);
-	temp |= TPI_RW_EN_SRC_TERMIN;
-	dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1);
-
-	/* Set TPI system control */
-	temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
-	dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1);
-
-	/* Set pixel clock */
-	temp1 = PICOS2KHZ(videomode->pixclock) / 10;
-	temp = (u8)(temp1 & 0xFF);
-	dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1);
-	temp = (u8)(temp1 >> 8);
-	dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1);
-
-	/* Set total pixels per line */
-	temp1 = videomode->hsync_len + videomode->left_margin +
-		videomode->xres + videomode->right_margin;
-	temp = (u8)(temp1 & 0xFF);
-	dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1);
-	temp = (u8)(temp1 >> 8);
-	dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1);
-
-	/* Set total lines */
-	temp2 = videomode->vsync_len + videomode->upper_margin +
-		videomode->yres + videomode->lower_margin;
-	temp = (u8)(temp2 & 0xFF);
-	dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1);
-	temp = (u8)(temp2 >> 8);
-	dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1);
-
-	/* Set vertical frequency in Hz */
-	temp3 = temp1 * temp2;
-	temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
-	temp1 = (u16)temp3 * 100;
-	temp = (u8)(temp1 & 0xFF);
-	dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1);
-	temp = (u8)(temp1 >> 8);
-	dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1);
-
-	/* Set TPI input bus and pixel repetition data */
-	temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
-		TPI_INBUS_RISING_EDGE;
-	dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1);
-
-	/* Set TPI AVI Input format data */
-	temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
-		TPI_INPUT_CLR_RGB;
-	dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1);
-
-	/* Set TPI AVI Output format data */
-	temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
-		TPI_OUTPUT_CLR_HDMI_RGB;
-	dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1);
-
-	/* Set TPI audio configuration write data */
-	temp = TPI_AUDIO_PASS_BASIC;
-	dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1);
-
-	temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
-		TPI_AUDIO_TYPE_PCM;
-	dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1);
-
-	temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
-	dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1);
-#else
-	i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
-
-	/* Enable TPI transmitter mode */
-	temp = TPI_TRANS_MODE_ENABLE;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1);
-
-	/* Enter into D0 state, full operation */
-	i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
-	temp &= ~TPI_PWR_STAT_MASK;
-	temp |= TPI_PWR_STAT_D0;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
-
-	/* Enable source termination */
-	temp = TPI_SET_PAGE_SII9022A;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1);
-	temp = TPI_SET_OFFSET_SII9022A;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1);
-
-	i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
-	temp |= TPI_RW_EN_SRC_TERMIN;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
-
-	/* Set TPI system control */
-	temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1);
-
-	/* Set pixel clock */
-	temp1 = PICOS2KHZ(videomode->pixclock) / 10;
-	temp = (u8)(temp1 & 0xFF);
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1);
-	temp = (u8)(temp1 >> 8);
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1);
-
-	/* Set total pixels per line */
-	temp1 = videomode->hsync_len + videomode->left_margin +
-		videomode->xres + videomode->right_margin;
-	temp = (u8)(temp1 & 0xFF);
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1);
-	temp = (u8)(temp1 >> 8);
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1);
-
-	/* Set total lines */
-	temp2 = videomode->vsync_len + videomode->upper_margin +
-		videomode->yres + videomode->lower_margin;
-	temp = (u8)(temp2 & 0xFF);
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1);
-	temp = (u8)(temp2 >> 8);
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1);
-
-	/* Set vertical frequency in Hz */
-	temp3 = temp1 * temp2;
-	temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
-	temp1 = (u16)temp3 * 100;
-	temp = (u8)(temp1 & 0xFF);
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1);
-	temp = (u8)(temp1 >> 8);
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1);
-
-	/* Set TPI input bus and pixel repetition data */
-	temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
-		TPI_INBUS_RISING_EDGE;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1);
-
-	/* Set TPI AVI Input format data */
-	temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
-		TPI_INPUT_CLR_RGB;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1);
-
-	/* Set TPI AVI Output format data */
-	temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
-		TPI_OUTPUT_CLR_HDMI_RGB;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1);
-
-	/* Set TPI audio configuration write data */
-	temp = TPI_AUDIO_PASS_BASIC;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1);
-
-	temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
-		TPI_AUDIO_TYPE_PCM;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1);
-
-	temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
-	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1);
-#endif
-
-	return 0;
-}
diff --git a/board/freescale/common/dcu_sii9022a.h b/board/freescale/common/dcu_sii9022a.h
deleted file mode 100644
index 7851775..0000000
--- a/board/freescale/common/dcu_sii9022a.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DCU_HDMI_SII9022A__
-#define __DCU_HDMI_SII9022A__
-
-/* Programming of Silicon SII9022A connector HDMI Transmitter*/
-int dcu_set_dvi_encoder(struct fb_videomode *videomode);
-
-#endif
diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c
deleted file mode 100644
index 05e6a3a..0000000
--- a/board/freescale/common/diu_ch7301.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
- * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
- *	    Wang Dongsheng <dongsheng.wang@freescale.com>
- *
- * This file is copied and modified from the original t1040qds/diu.c.
- * Encoder can be used in T104x and LSx Platform.
- */
-
-#include <common.h>
-#include <stdio_dev.h>
-#include <i2c.h>
-#include <linux/delay.h>
-
-#define I2C_DVI_INPUT_DATA_FORMAT_REG		0x1F
-#define I2C_DVI_PLL_CHARGE_CNTL_REG		0x33
-#define I2C_DVI_PLL_DIVIDER_REG			0x34
-#define I2C_DVI_PLL_SUPPLY_CNTL_REG		0x35
-#define I2C_DVI_PLL_FILTER_REG			0x36
-#define I2C_DVI_TEST_PATTERN_REG		0x48
-#define I2C_DVI_POWER_MGMT_REG			0x49
-#define I2C_DVI_LOCK_STATE_REG			0x4D
-#define I2C_DVI_SYNC_POLARITY_REG		0x56
-
-/*
- * Set VSYNC/HSYNC to active high. This is polarity of sync signals
- * from DIU->DVI. The DIU default is active igh, so DVI is set to
- * active high.
- */
-#define I2C_DVI_INPUT_DATA_FORMAT_VAL		0x98
-
-#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL	0x06
-#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL	0x26
-#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL	0xA0
-#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL	0x08
-#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL	0x16
-#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL	0x60
-
-/* Clear test pattern */
-#define I2C_DVI_TEST_PATTERN_VAL		0x18
-/* Exit Power-down mode */
-#define I2C_DVI_POWER_MGMT_VAL			0xC0
-
-/* Monitor polarity is handled via DVI Sync Polarity Register */
-#define I2C_DVI_SYNC_POLARITY_VAL		0x00
-
-/* Programming of HDMI Chrontel CH7301 connector */
-int diu_set_dvi_encoder(unsigned int pixclock)
-{
-	int ret;
-	u8 temp;
-
-	temp = I2C_DVI_TEST_PATTERN_VAL;
-#if CONFIG_IS_ENABLED(DM_I2C)
-	struct udevice *dev;
-
-	ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
-				      CONFIG_SYS_I2C_DVI_ADDR,
-				      1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       CONFIG_SYS_I2C_DVI_BUS_NUM);
-		return ret;
-	}
-	ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select proper dvi test pattern\n");
-		return ret;
-	}
-	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi input data format\n");
-		return ret;
-	}
-
-	/* Set Sync polarity register */
-	temp = I2C_DVI_SYNC_POLARITY_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi syc polarity\n");
-		return ret;
-	}
-
-	/* Set PLL registers based on pixel clock rate*/
-	if (pixclock > 65000000) {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	} else {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	}
-
-	temp = I2C_DVI_POWER_MGMT_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi power mgmt\n");
-		return ret;
-	}
-#else
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select proper dvi test pattern\n");
-		return ret;
-	}
-	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
-			1, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi input data format\n");
-		return ret;
-	}
-
-	/* Set Sync polarity register */
-	temp = I2C_DVI_SYNC_POLARITY_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi syc polarity\n");
-		return ret;
-	}
-
-	/* Set PLL registers based on pixel clock rate*/
-	if (pixclock > 65000000) {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_CHARGE_CNTL_REG, 1,	&temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	} else {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	}
-
-	temp = I2C_DVI_POWER_MGMT_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi power mgmt\n");
-		return ret;
-	}
-#endif
-
-	udelay(500);
-
-	return 0;
-}
diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h
deleted file mode 100644
index f35661c..0000000
--- a/board/freescale/common/diu_ch7301.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DIU_HDMI_CH7301__
-#define __DIU_HDMI_CH7301__
-
-/* Programming of HDMI Chrontel CH7301 connector */
-int diu_set_dvi_encoder(unsigned int pixclock);
-
-#endif
diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile
index bec151f..587bbd7 100644
--- a/board/freescale/ls1021aiot/Makefile
+++ b/board/freescale/ls1021aiot/Makefile
@@ -3,5 +3,4 @@
 # Copyright 2016 Freescale Semiconductor, Inc.
 
 obj-y += ls1021aiot.o
-obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c
deleted file mode 100644
index e4fbcbc..0000000
--- a/board/freescale/ls1021aiot/dcu.c
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * FSL DCU Framebuffer driver
- */
-
-#include <common.h>
-#include <fsl_dcu_fb.h>
-#include <asm/global_data.h>
-#include "div64.h"
-#include "../common/dcu_sii9022a.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned int dcu_set_pixel_clock(unsigned int pixclock)
-{
-	unsigned long long div;
-
-	div = (unsigned long long)(gd->bus_clk / 1000);
-	div *= (unsigned long long)pixclock;
-	do_div(div, 1000000000);
-
-	return div;
-}
-
-int platform_dcu_init(struct fb_info *fbinfo,
-		      unsigned int xres, unsigned int yres,
-		      const char *port,
-		      struct fb_videomode *dcu_fb_videomode)
-{
-	const char *name;
-	unsigned int pixel_format;
-
-	if (strncmp(port, "twr_lcd", 4) == 0) {
-		name = "TWR_LCD_RGB card";
-	} else {
-		name = "HDMI";
-		dcu_set_dvi_encoder(dcu_fb_videomode);
-	}
-
-	printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
-
-	pixel_format = 32;
-	fsl_dcu_init(fbinfo, xres, yres, pixel_format);
-
-	return 0;
-}
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index 1e50e46..6503034 100644
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -7,5 +7,4 @@
 obj-y += ls1021aqds.o
 obj-y += ddr.o
 obj-y += eth.o
-obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
deleted file mode 100644
index b5fee06..0000000
--- a/board/freescale/ls1021aqds/dcu.c
+++ /dev/null
@@ -1,110 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
- *
- * FSL DCU Framebuffer driver
- */
-
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <common.h>
-#include <fsl_dcu_fb.h>
-#include <i2c.h>
-#include "../common/i2c_mux.h"
-#include "div64.h"
-#include "../common/diu_ch7301.h"
-#include "ls1021aqds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned int dcu_set_pixel_clock(unsigned int pixclock)
-{
-	unsigned long long div;
-
-	div = (unsigned long long)(gd->bus_clk / 1000);
-	div *= (unsigned long long)pixclock;
-	do_div(div, 1000000000);
-
-	return div;
-}
-
-int platform_dcu_init(struct fb_info *fbinfo,
-		      unsigned int xres,
-		      unsigned int yres,
-		      const char *port,
-		      struct fb_videomode *dcu_fb_videomode)
-{
-	const char *name;
-	unsigned int pixel_format;
-	int ret;
-	u8 ch;
-
-	/* Mux I2C3+I2C4 as HSYNC+VSYNC */
-#if CONFIG_IS_ENABLED(DM_I2C)
-	struct udevice *dev;
-
-	/* QIXIS device mount on I2C1 bus*/
-	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
-				      1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       0);
-		return ret;
-	}
-	ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
-	if (ret) {
-		printf("Error: failed to read I2C @%02x\n",
-		       CONFIG_SYS_I2C_QIXIS_ADDR);
-		return ret;
-	}
-	ch &= 0x1F;
-	ch |= 0xA0;
-	ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
-
-#else
-	ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
-		       1, &ch, 1);
-	if (ret) {
-		printf("Error: failed to read I2C @%02x\n",
-		       CONFIG_SYS_I2C_QIXIS_ADDR);
-		return ret;
-	}
-	ch &= 0x1F;
-	ch |= 0xA0;
-	ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
-			1, &ch, 1);
-#endif
-	if (ret) {
-		printf("Error: failed to write I2C @%02x\n",
-		       CONFIG_SYS_I2C_QIXIS_ADDR);
-		return ret;
-	}
-
-	if (strncmp(port, "hdmi", 4) == 0) {
-		unsigned long pixval;
-
-		name = "HDMI";
-
-		pixval = 1000000000 / dcu_fb_videomode->pixclock;
-		pixval *= 1000;
-
-#if !CONFIG_IS_ENABLED(DM_I2C)
-		i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
-#endif
-		select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
-				      CONFIG_SYS_I2C_DVI_BUS_NUM);
-		diu_set_dvi_encoder(pixval);
-		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT,
-				      CONFIG_SYS_I2C_DVI_BUS_NUM);
-	} else {
-		return 0;
-	}
-
-	printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
-
-	pixel_format = 32;
-	fsl_dcu_init(fbinfo, xres, yres, pixel_format);
-
-	return 0;
-}
diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile
index d9a2f52..cfa6c0c 100644
--- a/board/freescale/ls1021atwr/Makefile
+++ b/board/freescale/ls1021atwr/Makefile
@@ -5,5 +5,4 @@
 #
 
 obj-y += ls1021atwr.o
-obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c
deleted file mode 100644
index 7bf283e..0000000
--- a/board/freescale/ls1021atwr/dcu.c
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * FSL DCU Framebuffer driver
- */
-
-#include <common.h>
-#include <fsl_dcu_fb.h>
-#include <asm/global_data.h>
-#include "div64.h"
-#include "../common/dcu_sii9022a.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned int dcu_set_pixel_clock(unsigned int pixclock)
-{
-	unsigned long long div;
-
-	div = (unsigned long long)(gd->bus_clk / 1000);
-	div *= (unsigned long long)pixclock;
-	do_div(div, 1000000000);
-
-	return div;
-}
-
-int platform_dcu_init(struct fb_info *fbinfo,
-		      unsigned int xres, unsigned int yres,
-		      const char *port,
-		      struct fb_videomode *dcu_fb_videomode)
-{
-	const char *name;
-	unsigned int pixel_format;
-
-	if (strncmp(port, "twr_lcd", 4) == 0) {
-		name = "TWR_LCD_RGB card";
-	} else {
-		name = "HDMI";
-		dcu_set_dvi_encoder(dcu_fb_videomode);
-	}
-
-	printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
-
-	pixel_format = 32;
-	fsl_dcu_init(fbinfo, xres, yres, pixel_format);
-
-	return 0;
-}
diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile
index 1a9581c..808e350 100644
--- a/board/freescale/mx51evk/Makefile
+++ b/board/freescale/mx51evk/Makefile
@@ -5,4 +5,3 @@
 # (C) Copyright 2009 Freescale Semiconductor, Inc.
 
 obj-y			+= mx51evk.o
-obj-$(CONFIG_VIDEO)	+= mx51evk_video.o
diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile
index d2ebd94..9befe42 100644
--- a/board/freescale/mx53loco/Makefile
+++ b/board/freescale/mx53loco/Makefile
@@ -4,4 +4,3 @@
 # Jason Liu <r64343@freescale.com>
 
 obj-y			+= mx53loco.o
-obj-$(CONFIG_VIDEO)	+= mx53loco_video.o
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
index d67e941..a949501 100644
--- a/board/freescale/t104xrdb/Makefile
+++ b/board/freescale/t104xrdb/Makefile
@@ -8,7 +8,6 @@ else
 obj-y	+= t104xrdb.o
 obj-y	+= cpld.o
 obj-y	+= eth.o
-obj-$(CONFIG_FSL_DIU_FB)+= diu.o
 endif
 obj-y	+= ddr.o
 obj-y	+= law.o
diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c
deleted file mode 100644
index 25c8597..0000000
--- a/board/freescale/t104xrdb/diu.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
- */
-
-#include <clock_legacy.h>
-#include <asm/io.h>
-#include <common.h>
-#include <command.h>
-#include <fsl_diu_fb.h>
-#include <linux/ctype.h>
-#include <video_fb.h>
-
-#include "../common/diu_ch7301.h"
-
-#include "cpld.h"
-#include "t104xrdb.h"
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register. So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F		0x10000000
-#define AD_ALPHA_C_SHIFT	25
-#define AD_BLUE_C_SHIFT		23
-#define AD_GREEN_C_SHIFT	21
-#define AD_RED_C_SHIFT		19
-#define AD_PIXEL_S_SHIFT	16
-#define AD_COMP_3_SHIFT		12
-#define AD_COMP_2_SHIFT		8
-#define AD_COMP_1_SHIFT		4
-#define AD_COMP_0_SHIFT		0
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	unsigned long speed_ccb, temp;
-	u32 pixval;
-	int ret;
-
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000 / pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-
-	/* Program HDMI encoder */
-	ret = diu_set_dvi_encoder(temp);
-	if (ret) {
-		puts("Failed to set DVI encoder\n");
-		return;
-	}
-
-	/* Program pixel clock */
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-
-	/* enable clock*/
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	u32 pixel_format;
-	u8 sw;
-
-	/*Configure Display ouput port as HDMI*/
-	sw = CPLD_READ(sfp_ctl_status);
-	CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
-
-	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
-		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
-		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
-		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
-		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
-	printf("DIU: Switching to monitor DVI @ %ux%u\n",  xres, yres);
-
-	return fsl_diu_init(xres, yres, pixel_format, 0);
-}
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index 3d22f20..24c0fb2 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -379,30 +379,7 @@ static void novena_spl_setup_iomux_uart(void)
 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 }
 
-/*
- * Video
- */
-#ifdef CONFIG_VIDEO
-static iomux_v3_cfg_t hdmi_pads[] = {
-	/* "Ghost HPD" pin */
-	MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
-	/* LCD_PWR_CTL */
-	MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LCD_BL_ON */
-	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* GPIO_PWM1 */
-	MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void novena_spl_setup_iomux_video(void)
-{
-	imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
-	gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
-}
-#else
 static inline void novena_spl_setup_iomux_video(void) {}
-#endif
 
 /*
  * SPL boots from uSDHC card
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 5628366..85025f2 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -96,9 +96,6 @@ int board_init(void)
 #ifdef CONFIG_NAND_CS_INIT
 	board_nand_cs_init();
 #endif
-#ifdef CONFIG_VIDEO
-	board_video_init();
-#endif
 
 	return 0;
 }
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index fba678b..4e36a6f 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -276,13 +276,6 @@ int factoryset_read_eeprom(int i2c_addr)
 	printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
 	       factory_dat.usb_product_id);
 #endif
-#if defined(CONFIG_VIDEO)
-	if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
-					(uchar *)"name", factory_dat.disp_name,
-					MAX_STRING_LENGTH)) {
-		debug("display name: %s\n", factory_dat.disp_name);
-	}
-#endif
 	if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
 					(uchar *)"num", factory_dat.serial,
 					MAX_STRING_LENGTH)) {
diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h
index 261a217..8fa6c3b 100644
--- a/board/siemens/common/factoryset.h
+++ b/board/siemens/common/factoryset.h
@@ -17,9 +17,6 @@ struct factorysetcontainer {
 	int usb_vendor_id;
 	int usb_product_id;
 	int pxm50;
-#if defined(CONFIG_VIDEO)
-	unsigned char disp_name[MAX_STRING_LENGTH];
-#endif
 	unsigned char serial[MAX_STRING_LENGTH];
 	int version;
 	uchar asn[MAX_STRING_LENGTH];
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index de52838..47f19bc 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -28,7 +28,6 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
-#include "../../../drivers/video/da8xx-fb.h"
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
@@ -243,194 +242,6 @@ int board_eth_init(struct bd_info *bis)
 }
 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-static struct da8xx_panel lcd_panels[] = {
-	/* AUO G156XW01 V1 */
-	[0] = {
-		.name = "AUO_G156XW01_V1",
-		.width = 1376,
-		.height = 768,
-		.hfp = 14,
-		.hbp = 64,
-		.hsw = 56,
-		.vfp = 1,
-		.vbp = 28,
-		.vsw = 3,
-		.pxl_clk = 60000000,
-		.invert_pxl_clk = 0,
-	},
-	/* AUO B101EVN06 V0 */
-	[1] = {
-		.name = "AUO_B101EVN06_V0",
-		.width = 1280,
-		.height = 800,
-		.hfp = 52,
-		.hbp = 84,
-		.hsw = 36,
-		.vfp = 3,
-		.vbp = 14,
-		.vsw = 6,
-		.pxl_clk = 60000000,
-		.invert_pxl_clk = 0,
-	},
-	/*
-	 * Settings from factoryset
-	 * stored in EEPROM
-	 */
-	[2] = {
-		.name = "factoryset",
-		.width = 0,
-		.height = 0,
-		.hfp = 0,
-		.hbp = 0,
-		.hsw = 0,
-		.vfp = 0,
-		.vbp = 0,
-		.vsw = 0,
-		.pxl_clk = 60000000,
-		.invert_pxl_clk = 0,
-	},
-};
-
-static const struct display_panel disp_panel = {
-	WVGA,
-	32,
-	16,
-	COLOR_ACTIVE,
-};
-
-static const struct lcd_ctrl_config lcd_cfg = {
-	&disp_panel,
-	.ac_bias		= 255,
-	.ac_bias_intrpt		= 0,
-	.dma_burst_sz		= 16,
-	.bpp			= 32,
-	.fdd			= 0x80,
-	.tft_alt_mode		= 0,
-	.stn_565_mode		= 0,
-	.mono_8bit_mode		= 0,
-	.invert_line_clock	= 1,
-	.invert_frm_clock	= 1,
-	.sync_edge		= 0,
-	.sync_ctrl		= 1,
-	.raster_order		= 0,
-};
-
-static int set_gpio(int gpio, int state)
-{
-	gpio_request(gpio, "temp");
-	gpio_direction_output(gpio, state);
-	gpio_set_value(gpio, state);
-	gpio_free(gpio);
-	return 0;
-}
-
-static int enable_backlight(void)
-{
-	set_gpio(BOARD_LCD_POWER, 1);
-	set_gpio(BOARD_BACK_LIGHT, 1);
-	set_gpio(BOARD_TOUCH_POWER, 1);
-	return 0;
-}
-
-static int enable_pwm(void)
-{
-	struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
-	struct pwmss_ecap_regs *ecap;
-	int ticks = PWM_TICKS;
-	int duty = PWM_DUTY;
-
-	ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
-	/* enable clock */
-	setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
-	/* TimeStam Counter register */
-	writel(0xdb9, &ecap->tsctr);
-	/* config period */
-	writel(ticks - 1, &ecap->cap3);
-	writel(ticks - 1, &ecap->cap1);
-	setbits_le16(&ecap->ecctl2,
-		     (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
-	/* config duty */
-	writel(duty, &ecap->cap2);
-	writel(duty, &ecap->cap4);
-	/* start */
-	setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
-	return 0;
-}
-
-static struct dpll_regs dpll_lcd_regs = {
-	.cm_clkmode_dpll = CM_WKUP + 0x98,
-	.cm_idlest_dpll = CM_WKUP + 0x48,
-	.cm_clksel_dpll = CM_WKUP + 0x54,
-};
-
-/* no console on this board */
-int board_cfb_skip(void)
-{
-	return 1;
-}
-
-#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
-#define PLL_GET_N(v) (v & 0x7f)
-
-static int get_clk(struct dpll_regs *dpll_regs)
-{
-	unsigned int val;
-	unsigned int m, n;
-	int f = 0;
-
-	val = readl(dpll_regs->cm_clksel_dpll);
-	m = PLL_GET_M(val);
-	n = PLL_GET_N(val);
-	f = (m * V_OSCK) / n;
-
-	return f;
-};
-
-int clk_get(int clk)
-{
-	return get_clk(&dpll_lcd_regs);
-};
-
-static int conf_disp_pll(int m, int n)
-{
-	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-	struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
-
-	u32 *const clk_domains[] = {
-		&cmper->lcdclkctrl,
-		0
-	};
-	u32 *const clk_modules_explicit_en[] = {
-		&cmper->lcdclkctrl,
-		&cmper->lcdcclkstctrl,
-		&cmper->epwmss0clkctrl,
-		0
-	};
-	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
-	writel(0x0, &cmdpll->clklcdcpixelclk);
-
-	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
-
-	return 0;
-}
-
-static int board_video_init(void)
-{
-	conf_disp_pll(24, 1);
-	if (factory_dat.pxm50)
-		da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
-	else
-		da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
-
-	enable_pwm();
-	enable_backlight();
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index e0f232d..a8b196a 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -37,7 +37,6 @@
 #include <linux/delay.h>
 #include "board.h"
 #include "../common/factoryset.h"
-#include "../../../drivers/video/da8xx-fb.h"
 
 /*
  * Read header information from EEPROM into global structure.
@@ -224,252 +223,6 @@ void hw_watchdog_init(void)
 }
 #endif /* defined(CONFIG_HW_WATCHDOG) */
 
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-static struct da8xx_panel lcd_panels[] = {
-	/* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
-	[0] = {
-		.name   = "KWH043MC17-F01",
-		.width  = 480,
-		.height = 800,
-		.hfp = 50,              /* no spec, "don't care" values */
-		.hbp = 50,
-		.hsw = 50,
-		.vfp = 50,
-		.vbp = 50,
-		.vsw = 50,
-		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
-		.invert_pxl_clk = 1,
-	},
-	/* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
-	[1] = {
-		.name   = "KWH043ST20-F01",
-		.width  = 480,
-		.height = 800,
-		.hfp = 50,              /* no spec, "don't care" values */
-		.hbp = 50,
-		.hsw = 50,
-		.vfp = 50,
-		.vbp = 50,
-		.vsw = 50,
-		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
-		.invert_pxl_clk = 1,
-	},
-	/* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
-	[2] = {
-		.name   = "MI0430VT-1",
-		.width  = 480,
-		.height = 800,
-		.hfp = 50,              /* no spec, "don't care" values */
-		.hbp = 50,
-		.hsw = 50,
-		.vfp = 50,
-		.vbp = 50,
-		.vsw = 50,
-		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
-		.invert_pxl_clk = 1,
-	},
-};
-
-static const struct display_panel disp_panels[] = {
-	[0] = {
-		WVGA,
-		16,	/* RGB 888 */
-		16,
-		COLOR_ACTIVE,
-	},
-	[1] = {
-		WVGA,
-		16,	/* RGB 888 */
-		16,
-		COLOR_ACTIVE,
-	},
-	[2] = {
-		WVGA,
-		24,	/* RGB 888 */
-		16,
-		COLOR_ACTIVE,
-	},
-};
-
-static const struct lcd_ctrl_config lcd_cfgs[] = {
-	[0] = {
-		&disp_panels[0],
-		.ac_bias		= 255,
-		.ac_bias_intrpt		= 0,
-		.dma_burst_sz		= 16,
-		.bpp			= 16,
-		.fdd			= 0x80,
-		.tft_alt_mode		= 0,
-		.stn_565_mode		= 0,
-		.mono_8bit_mode		= 0,
-		.invert_line_clock	= 1,
-		.invert_frm_clock	= 1,
-		.sync_edge		= 0,
-		.sync_ctrl		= 1,
-		.raster_order		= 0,
-	},
-	[1] = {
-		&disp_panels[1],
-		.ac_bias		= 255,
-		.ac_bias_intrpt		= 0,
-		.dma_burst_sz		= 16,
-		.bpp			= 16,
-		.fdd			= 0x80,
-		.tft_alt_mode		= 0,
-		.stn_565_mode		= 0,
-		.mono_8bit_mode		= 0,
-		.invert_line_clock	= 1,
-		.invert_frm_clock	= 1,
-		.sync_edge		= 0,
-		.sync_ctrl		= 1,
-		.raster_order		= 0,
-	},
-	[2] = {
-		&disp_panels[2],
-		.ac_bias		= 255,
-		.ac_bias_intrpt		= 0,
-		.dma_burst_sz		= 16,
-		.bpp			= 24,
-		.fdd			= 0x80,
-		.tft_alt_mode		= 0,
-		.stn_565_mode		= 0,
-		.mono_8bit_mode		= 0,
-		.invert_line_clock	= 1,
-		.invert_frm_clock	= 1,
-		.sync_edge		= 0,
-		.sync_ctrl		= 1,
-		.raster_order		= 0,
-	},
-
-};
-
-/* no console on this board */
-int board_cfb_skip(void)
-{
-	return 1;
-}
-
-#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
-#define PLL_GET_N(v) (v & 0x7f)
-
-static struct dpll_regs dpll_lcd_regs = {
-	.cm_clkmode_dpll = CM_WKUP + 0x98,
-	.cm_idlest_dpll = CM_WKUP + 0x48,
-	.cm_clksel_dpll = CM_WKUP + 0x54,
-};
-
-static int get_clk(struct dpll_regs *dpll_regs)
-{
-	unsigned int val;
-	unsigned int m, n;
-	int f = 0;
-
-	val = readl(dpll_regs->cm_clksel_dpll);
-	m = PLL_GET_M(val);
-	n = PLL_GET_N(val);
-	f = (m * V_OSCK) / n;
-
-	return f;
-};
-
-int clk_get(int clk)
-{
-	return get_clk(&dpll_lcd_regs);
-};
-
-static int conf_disp_pll(int m, int n)
-{
-	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
-#if defined(DISPL_PLL_SPREAD_SPECTRUM)
-	struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-#endif
-
-	u32 *const clk_domains[] = {
-		&cmper->lcdclkctrl,
-		0
-	};
-	u32 *const clk_modules_explicit_en[] = {
-		&cmper->lcdclkctrl,
-		&cmper->lcdcclkstctrl,
-		&cmper->spi1clkctrl,
-		0
-	};
-	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
-
-	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
-
-#if defined(DISPL_PLL_SPREAD_SPECTRUM)
-	writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
-	writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
-	writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
-	       &cmwkup->clkmoddplldisp); /* 0x98 */
-#endif
-	return 0;
-}
-
-static int set_gpio(int gpio, int state)
-{
-	gpio_request(gpio, "temp");
-	gpio_direction_output(gpio, state);
-	gpio_set_value(gpio, state);
-	gpio_free(gpio);
-	return 0;
-}
-
-static int enable_lcd(void)
-{
-	unsigned char buf[1];
-
-	set_gpio(BOARD_LCD_RESET, 0);
-	mdelay(1);
-	set_gpio(BOARD_LCD_RESET, 1);
-	mdelay(1);
-
-	/* spi lcd init */
-	kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
-
-	/* backlight on */
-	buf[0] = 0xf;
-	i2c_write(0x24, 0x7, 1, buf, 1);
-	buf[0] = 0x3f;
-	i2c_write(0x24, 0x8, 1, buf, 1);
-	return 0;
-}
-
-int arch_early_init_r(void)
-{
-	enable_lcd();
-	return 0;
-}
-
-static int board_video_init(void)
-{
-	int i;
-	int anzdisp = ARRAY_SIZE(lcd_panels);
-	int display = 1;
-
-	for (i = 0; i < anzdisp; i++) {
-		if (strncmp((const char *)factory_dat.disp_name,
-			    lcd_panels[i].name,
-		    strlen((const char *)factory_dat.disp_name)) == 0) {
-			printf("DISPLAY: %s\n", factory_dat.disp_name);
-			break;
-		}
-	}
-	if (i == anzdisp) {
-		i = 1;
-		printf("%s: %s not found, using default %s\n", __func__,
-		       factory_dat.disp_name, lcd_panels[i].name);
-	}
-	conf_disp_pll(24, 1);
-	da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
-			 lcd_cfgs[display].bpp);
-
-	return 0;
-}
-#endif /* ifdef CONFIG_VIDEO */
-
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index f6a3cc1..3430a1e 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -26,7 +26,6 @@
 #include <fdt_support.h>
 #include <asm/io.h>
 #include <i2c.h>
-#include <video_fb.h>
 #include "upm_table.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile
index 6272a77..9be2cbc 100644
--- a/board/toradex/colibri_vf/Makefile
+++ b/board/toradex/colibri_vf/Makefile
@@ -3,4 +3,3 @@
 # Copyright 2013 Freescale Semiconductor, Inc.
 
 obj-y	:= colibri_vf.o
-obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index c09591e..dcef2db 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -19,7 +19,6 @@
 #include <asm/io.h>
 #include <env.h>
 #include <fdt_support.h>
-#include <fsl_dcu_fb.h>
 #include <g_dnl.h>
 #include <jffs2/load_kernel.h>
 #include <mtd_node.h>
@@ -205,49 +204,6 @@ static void setup_iomux_gpio(void)
 }
 #endif
 
-#ifdef CONFIG_VIDEO_FSL_DCU_FB
-static void setup_iomux_fsl_dcu(void)
-{
-	static const iomux_v3_cfg_t dcu0_pads[] = {
-		VF610_PAD_PTE0__DCU0_HSYNC,
-		VF610_PAD_PTE1__DCU0_VSYNC,
-		VF610_PAD_PTE2__DCU0_PCLK,
-		VF610_PAD_PTE4__DCU0_DE,
-		VF610_PAD_PTE5__DCU0_R0,
-		VF610_PAD_PTE6__DCU0_R1,
-		VF610_PAD_PTE7__DCU0_R2,
-		VF610_PAD_PTE8__DCU0_R3,
-		VF610_PAD_PTE9__DCU0_R4,
-		VF610_PAD_PTE10__DCU0_R5,
-		VF610_PAD_PTE11__DCU0_R6,
-		VF610_PAD_PTE12__DCU0_R7,
-		VF610_PAD_PTE13__DCU0_G0,
-		VF610_PAD_PTE14__DCU0_G1,
-		VF610_PAD_PTE15__DCU0_G2,
-		VF610_PAD_PTE16__DCU0_G3,
-		VF610_PAD_PTE17__DCU0_G4,
-		VF610_PAD_PTE18__DCU0_G5,
-		VF610_PAD_PTE19__DCU0_G6,
-		VF610_PAD_PTE20__DCU0_G7,
-		VF610_PAD_PTE21__DCU0_B0,
-		VF610_PAD_PTE22__DCU0_B1,
-		VF610_PAD_PTE23__DCU0_B2,
-		VF610_PAD_PTE24__DCU0_B3,
-		VF610_PAD_PTE25__DCU0_B4,
-		VF610_PAD_PTE26__DCU0_B5,
-		VF610_PAD_PTE27__DCU0_B6,
-		VF610_PAD_PTE28__DCU0_B7,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
-}
-
-static void setup_tcon(void)
-{
-	setbits_le32(TCON0_BASE_ADDR, (1 << 29));
-}
-#endif
-
 static inline int is_colibri_vf61(void)
 {
 	struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
@@ -353,11 +309,6 @@ static void clock_init(void)
 			CCM_CSCDR3_NFC_PRE_DIV(3));
 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 			CCM_CSCMR2_RMII_CLK_SEL(2));
-
-#ifdef CONFIG_VIDEO_FSL_DCU_FB
-		setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
-		setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
-#endif
 }
 
 static void mscm_init(void)
@@ -378,11 +329,6 @@ int board_early_init_f(void)
 	setup_iomux_gpio();
 #endif
 
-#ifdef CONFIG_VIDEO_FSL_DCU_FB
-	setup_tcon();
-	setup_iomux_fsl_dcu();
-#endif
-
 	return 0;
 }
 
@@ -433,9 +379,6 @@ int checkboard(void)
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
-	int ret = 0;
-#endif
 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 	static const struct node_info nodes[] = {
 		{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
@@ -445,11 +388,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	puts("   Updating MTD partitions...\n");
 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 #endif
-#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
-	ret = fsl_dcu_fixedfb_setup(blob);
-	if (ret)
-		return ret;
-#endif
 
 	return ft_common_board_setup(blob, bd);
 }
diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c
deleted file mode 100644
index c688ed7..0000000
--- a/board/toradex/colibri_vf/dcu.c
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2017 Toradex AG
- *
- * FSL DCU platform driver
- */
-
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <common.h>
-#include <fsl_dcu_fb.h>
-#include "div64.h"
-
-unsigned int dcu_set_pixel_clock(unsigned int pixclock)
-{
-	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
-	unsigned long long div;
-
-	clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
-	clrsetbits_le32(&ccm->cscdr3,
-			CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
-			CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
-	div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
-	do_div(div, pixclock);
-
-	return div;
-}
-
-int platform_dcu_init(struct fb_info *fbinfo,
-		      unsigned int xres,
-		      unsigned int yres,
-		      const char *port,
-		      struct fb_videomode *dcu_fb_videomode)
-{
-	fsl_dcu_init(fbinfo, xres, yres, 32);
-
-	return 0;
-}