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authorMarek Vasut <marex@denx.de>2020-04-29 15:08:38 +0200
committerPatrick Delaunay <patrick.delaunay@st.com>2020-05-14 09:02:12 +0200
commit92ca0f7446c5948f364bfb3377f9e08fad7ff857 (patch)
tree85f171a7fe1239f4b4e214becbcd5b8a01a08e78 /board
parent1ca501741831e3ab8366ddd4d7f74f27e5fe14c6 (diff)
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ARM: dts: stm32: Synchronize DDR setttings on DH SoMs
Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them into use by the board file instead of the default ones. These new DRAM settings are a better fit for the SoMs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'board')
-rw-r--r--board/dhelectronics/dh_stm32mp1/board.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index ec1edd5..85d56f6 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -177,12 +177,16 @@ static void board_get_coding_straps(void)
int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
const char *name)
{
+ if (ddr3code == 1 &&
+ !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
+ return 0;
+
if (ddr3code == 2 &&
- !strcmp(name, "st,ddr3-1066-888-bin-g-1x4gb-533mhz"))
+ !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
return 0;
if (ddr3code == 3 &&
- !strcmp(name, "st,ddr3-1066-888-bin-g-2x4gb-533mhz"))
+ !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
return 0;
return -EINVAL;