arm: kirkwood: Sheevaplug : Use Marvell uclass mvgbe and PHY driver for Ethernet

The Globalscale Technologies Sheevaplug board has the network chip
Marvell 88E1116R. Use uclass mvgbe and the compatible driver M88E1310
driver to bring up Ethernet.

- Remove CONFIG_RESET_PHY_R symbol from all board files
- Use uclass mvgbe to bring up the network. And remove ad-hoc code.
- Enable CONFIG_PHY_MARVELL to properly configure the network.
- Miscellaneous changes: Move constants to .c file and remove header file
board/Marvell/sheevaplug/sheevaplug.h, use BIT macro, and add/cleanup
comments.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>

2 files changed, 14 insertions, 93 deletions

diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index 5952d15..26ee39e 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2021  Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2021-2022  Tony Dinh <mibodhi@gmail.com>
  * (C) Copyright 2009
  * Marvell Semiconductor <www.marvell.com>
  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
@@ -8,17 +8,21 @@
 
 #include <common.h>
 #include <init.h>
-#include <miiphy.h>
-#include <net.h>
+#include <netdev.h>
 #include <asm/global_data.h>
 #include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
-#include "sheevaplug.h"
+#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define SHEEVAPLUG_OE_LOW		(~(0))
+#define SHEEVAPLUG_OE_HIGH		(~(0))
+#define SHEEVAPLUG_OE_VAL_LOW		BIT(29)       /* USB_PWEN low */
+#define SHEEVAPLUG_OE_VAL_HIGH		BIT(17)       /* LED pin high */
+
 int board_early_init_f(void)
 {
 	/*
@@ -88,6 +92,11 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int board_eth_init(struct bd_info *bis)
+{
+	return cpu_eth_init(bis);
+}
+
 int board_init(void)
 {
 	/*
@@ -95,72 +104,8 @@ int board_init(void)
 	 */
 	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
 
-	/* adress of boot parameters */
+	/* address of boot parameters */
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
-
-static int fdt_get_phy_addr(const char *path)
-{
-	const void *fdt = gd->fdt_blob;
-	const u32 *reg;
-	const u32 *val;
-	int node, phandle, addr;
-
-	/* Find the node by its full path */
-	node = fdt_path_offset(fdt, path);
-	if (node >= 0) {
-		/* Look up phy-handle */
-		val = fdt_getprop(fdt, node, "phy-handle", NULL);
-		if (val) {
-			phandle = fdt32_to_cpu(*val);
-			if (!phandle)
-				return -1;
-			/* Follow it to its node */
-			node = fdt_node_offset_by_phandle(fdt, phandle);
-			if (node) {
-				/* Look up reg */
-				reg = fdt_getprop(fdt, node, "reg", NULL);
-				if (reg) {
-					addr = fdt32_to_cpu(*reg);
-					return addr;
-				}
-			}
-		}
-	}
-	return -1;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
-	u16 reg;
-	int phyaddr;
-	char *name = "ethernet-controller@72000";
-	char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
-
-	if (miiphy_set_current_dev(name))
-		return;
-
-	phyaddr = fdt_get_phy_addr(eth0_path);
-	if (phyaddr < 0)
-		return;
-
-	/*
-	 * Enable RGMII delay on Tx and Rx for CPU port
-	 * Ref: sec 4.7.2 of chip datasheet
-	 */
-	miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
-	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
-	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
-	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
-	miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
-
-	/* reset the phy */
-	miiphy_reset(name, phyaddr);
-
-	printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h
deleted file mode 100644
index e026c1b..0000000
--- a/board/Marvell/sheevaplug/sheevaplug.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef __SHEEVAPLUG_H
-#define __SHEEVAPLUG_H
-
-#define SHEEVAPLUG_OE_LOW		(~(0))
-#define SHEEVAPLUG_OE_HIGH		(~(0))
-#define SHEEVAPLUG_OE_VAL_LOW		(1 << 29)	/* USB_PWEN low */
-#define SHEEVAPLUG_OE_VAL_HIGH		(1 << 17)	/* LED pin high */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG		10
-#define MV88E1116_CPRSP_CR3_REG		21
-#define MV88E1116_MAC_CTRL_REG		21
-#define MV88E1116_PGADR_REG		22
-#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
-
-#endif /* __SHEEVAPLUG_H */