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| author | Philippe Schenker <philippe.schenker@toradex.com> | 2022-04-08 10:07:11 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-04-12 19:10:44 +0200 |
| commit | aa6f57d87767089a8685ada55ca99e67c90a86d9 (patch) | |
| tree | dbcd22dcd20dcd99434942e6ae8547fc956a7a33 /board | |
| parent | f3b5100aff3a7edd53fd5d15bd6db92d294865e2 (diff) | |
| download | u-boot-aa6f57d87767089a8685ada55ca99e67c90a86d9.zip u-boot-aa6f57d87767089a8685ada55ca99e67c90a86d9.tar.gz u-boot-aa6f57d87767089a8685ada55ca99e67c90a86d9.tar.bz2 | |
board: colibri-imx6ull: fix detecting ethernet phy
Now that it is possible to use regulator-fixed-clock make use
of it. This makes U-Boot detect the PHY on first cold-boot.
This commit also adjusts the code in setup_fec and follows
how it is done in mx6ullevk.c
This commit also slows down the boot-process by about 150ms
as it now waits for the regulator-fixed-clock voltage that
drives the PHY to go up.
If you rely on very fast boot-speeds and don't need ethernet
for your boot-process you can safely revert the changes on
imx6ull-colibri.dtsi
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/toradex/colibri-imx6ull/colibri-imx6ull.c | 23 |
1 files changed, 8 insertions, 15 deletions
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 3244184..ba4e0df 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -100,28 +100,21 @@ static int setup_fec(void) struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; - /* provide the PHY clock from the i.MX 6 */ + /* + * Use 50MHz anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(1, ENET_50MHZ); if (ret) return ret; - /* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */ - clrsetbits_le32(&iomuxc_regs->gpr[1], - IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, - IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); - - /* give new Ethernet PHY power save mode circuitry time to settle */ - mdelay(300); + enable_enet_clk(1); return 0; } - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} #endif /* CONFIG_FEC_MXC */ int board_init(void) |