powerpc, 5xx: remove support for 5xx

There was for long time no activity in the 5xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 5xx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

9 files changed, 2 insertions, 1732 deletions

diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 5ea5a51..31636b3 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -28,10 +28,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_PATI)
-#define FIRM_START 0xFFF00000
-#endif
-
 extern int mem_test(ulong start, ulong ramsize, int quiet);
 
 #define I2C_BACKUP_ADDR 0x7C00		/* 0x200 bytes for backup */
@@ -189,11 +185,8 @@ mpl_prg(uchar *src, ulong size)
 	ulong start;
 	flash_info_t *info = &flash_info[0];
 	int i, rc;
-#if defined(CONFIG_PATI)
-	int start_sect;
-#endif
-#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
-		|| defined(CONFIG_TARGET_MIP405T) || defined(CONFIG_PATI)
+#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) || \
+	defined(CONFIG_TARGET_MIP405T)
 	char *copystr = (char *)src;
 	ulong *magic = (ulong *)src;
 
@@ -219,7 +212,6 @@ mpl_prg(uchar *src, ulong size)
 		printf("Wrong Firmware Image: %s\n", &copystr[i]);
 		return -1;
 	}
-#if !defined(CONFIG_PATI)
 	start = 0 - size;
 
 	/* unprotect sectors used by u-boot */
@@ -241,38 +233,6 @@ mpl_prg(uchar *src, ulong size)
 		flash_perror(rc);
 		return (1);
 	}
-
-#else /* #if !defined(CONFIG_PATI) */
-	start = FIRM_START;
-	start_sect = -1;
-
-	/* search start sector */
-	for (i = info->sector_count-1; i > 0; i--)
-		if (start >= info->start[i])
-			break;
-
-	start_sect = i;
-
-	for (i = info->sector_count-1; i > 0; i--)
-		if ((start + size) >= info->start[i])
-			break;
-
-	/* unprotect sectors used by u-boot */
-	flash_protect(FLAG_PROTECT_CLEAR,
-		      start,
-		      start + size,
-		      info);
-
-	/* now erase flash */
-	printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n",
-		start, start + size, start_sect, i,
-		info->start[start_sect], info->start[i]);
-	if ((rc = flash_erase (info, start_sect, i)) != 0) {
-		puts ("ERROR ");
-		flash_perror (rc);
-		return (1);
-	}
-#endif /* defined(CONFIG_PATI) */
 #endif
 	printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
 		(ulong)src, size);
@@ -380,7 +340,6 @@ mpl_prg_image(uchar *ld_addr)
 	return(rc);
 }
 
-#if !defined(CONFIG_PATI)
 void get_backup_values(backup_t *buf)
 {
 	i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
@@ -541,17 +500,13 @@ void check_env(void)
 	}
 }
 
-#endif /* #if !defined(CONFIG_PATI) */
-
 int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong ld_addr;
 	int result;
-#if !defined(CONFIG_PATI)
 	ulong size = IMAGE_SIZE;
 	ulong src = MULTI_PURPOSE_SOCKET_ADDR;
 	backup_t back;
-#endif
 
 	if (strcmp(argv[1], "flash") == 0)
 	{
@@ -587,15 +542,12 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			result=mpl_prg_image((uchar *)ld_addr);
 			return result;
 		}
-#if !defined(CONFIG_PATI)
 		if (strcmp(argv[2], "mps") == 0) {
 			puts("\nupdating bootloader image from MPS\n");
 			result=mpl_prg((uchar *)src,size);
 			return result;
 		}
-#endif /* #if !defined(CONFIG_PATI)	*/
 	}
-#if !defined(CONFIG_PATI)
 	if (strcmp(argv[1], "clearenvvalues") == 0)
 	{
 		if (strcmp(argv[2], "yes") == 0)
@@ -618,7 +570,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		set_backup_values(1);
 		return 0;
 	}
-#endif
 	return cmd_usage(cmdtp);
 }
 
diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig
deleted file mode 100644
index 0eeaf70..0000000
--- a/board/mpl/pati/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_PATI
-
-config SYS_BOARD
-	default "pati"
-
-config SYS_VENDOR
-	default "mpl"
-
-config SYS_CONFIG_NAME
-	default "PATI"
-
-config ISO_STRING
-	string
-	default "MEV-10084-001"
-endif
diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS
deleted file mode 100644
index 19ad05d..0000000
--- a/board/mpl/pati/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PATI BOARD
-#M:	-
-S:	Maintained
-F:	board/mpl/pati/
-F:	include/configs/PATI.h
-F:	configs/PATI_defconfig
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
deleted file mode 100644
index 9822082..0000000
--- a/board/mpl/pati/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:=  pati.o cmd_pati.o \
-		../common/common_util.o
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
deleted file mode 100644
index fcae5e0..0000000
--- a/board/mpl/pati/cmd_pati.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Adapted for PATI
- */
-
-#include <common.h>
-#include <command.h>
-#define PLX9056_LOC
-#include "plx9056.h"
-#include "pati.h"
-#include "pci_eeprom.h"
-
-extern void show_pld_regs(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-extern void user_led0(int led_on);
-extern void user_led1(int led_on);
-
-/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_SYS_PCI_CON_DEVICE)
-extern void pci_con_disc(void);
-extern void pci_con_connect(void);
-#endif
-
-/******************************************************************************
- * Eeprom Support
- ******************************************************************************/
-unsigned long get32(unsigned long addr)
-{
-	unsigned long *p=(unsigned long *)addr;
-	return *p;
-}
-
-void set32(unsigned long addr,unsigned long data)
-{
-	unsigned long *p=(unsigned long *)addr;
-	*p=data;
-}
-
-#define PCICFG_GET_REG(x)	(get32((x) + PCI_CONFIG_BASE))
-#define PCICFG_SET_REG(x,y)	(set32((x) + PCI_CONFIG_BASE,(y)))
-
-
-/******************************************************************************
- * reload_pci_eeprom
- ******************************************************************************/
-
-static void reload_pci_eeprom(void)
-{
-	unsigned long reg;
-	/* Set Bit 29 and clear it again */
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	udelay(1);
-	/* set it*/
-	reg|=(1<<29);
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	/* EECLK @ 33MHz = 125kHz
-	 * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
-	 * use 20msec
-	 */
-	udelay(20000); /* wait 20ms */
-	reg &= ~(1<<29); /* set it low */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	udelay(1); /* wait some time */
-}
-
-/******************************************************************************
- * clock_pci_eeprom
- ******************************************************************************/
-
-static void clock_pci_eeprom(void)
-{
-	unsigned long reg;
-	/* clock is low, data is valid */
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	udelay(1);
-	/* set clck high */
-	reg|=(1<<24);
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	udelay(1); /* wait some time */
-	reg &= ~(1<<24); /* set clock low */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	udelay(1); /* wait some time */
-}
-
-/******************************************************************************
- * send_pci_eeprom_cmd
- ******************************************************************************/
-static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len)
-{
-	unsigned long reg;
-	int i;
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	/* Clear all EEPROM bits */
-	reg &= ~(0xF << 24);
-	/* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	udelay(1); /* wait some time */
-	/* Enable EEPROM Chip Select */
-	reg |= (1 << 25);
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	/* Send EEPROM command - one bit at a time */
-	for (i = (int)(len-1); i >= 0; i--) {
-		/* Check if current bit is 0 or 1 */
-		if (cmd & (1 << i))
-			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
-		else
-			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-		clock_pci_eeprom();
-	}
-}
-
-/******************************************************************************
- * write_pci_eeprom_offs
- ******************************************************************************/
-static void write_pci_eeprom_offs(unsigned short offset, unsigned short value)
-{
-	unsigned long reg;
-	int bitpos, cmdshft, cmdlen, timeout;
-	/* we're using the Eeprom 93CS66 */
-	cmdshft  = 2;
-	cmdlen = EE66_CMD_LEN;
-	/* Send Write_Enable command to EEPROM */
-	send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen);
-	/* Send EEPROM Write command and offset to EEPROM */
-	send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen);
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	/* Clear all EEPROM bits */
-	reg &= ~(0xF << 24);
-	/* Make sure EEDO Input is disabled for some PLX chips */
-	reg &= ~(1 << 31);
-	/* Enable EEPROM Chip Select */
-	reg |= (1 << 25);
-	/* Write 16-bit value to EEPROM - one bit at a time */
-	for (bitpos = 15; bitpos >= 0; bitpos--) {
-		/* Get bit value and shift into result */
-		if (value & (1 << bitpos))
-			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
-		else
-			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg );
-		clock_pci_eeprom();
-	} /* for */
-	/* Deselect Chip */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25));
-	/* Re-select Chip */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25));
-	/* A small delay is needed to let EEPROM complete */
-	timeout = 0;
-	do {
-		udelay(10);
-		reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-		timeout++;
-	} while (((reg & (1 << 27)) == 0) && timeout < 20000);
-	/* Send Write_Disable command to EEPROM */
-	send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen);
-	/* Clear Chip Select and all other EEPROM bits */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
-}
-
-
-/******************************************************************************
- * read_pci_eeprom_offs
- ******************************************************************************/
-static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue)
-{
-	unsigned long reg;
-	int bitpos, cmdshft, cmdlen;
-	/* we're using the Eeprom 93CS66 */
-	cmdshft  = 2;
-	cmdlen = EE66_CMD_LEN;
-	/* Send EEPROM read command and offset to EEPROM */
-	send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen);
-	/* Set EEPROM write output bit */
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	/* Set EEDO Input enable */
-	reg |= (1 << 31);
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26));
-	/* Get 16-bit value from EEPROM - one bit at a time */
-	for (bitpos = 0; bitpos < 16; bitpos++) {
-		clock_pci_eeprom();
-		udelay(10);
-		reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-		/* Get bit value and shift into result */
-		if (reg & (1 << 27))
-			*pvalue = (unsigned short)((*pvalue << 1) | 1);
-		else
-			*pvalue = (unsigned short)(*pvalue << 1);
-	}
-	/* Clear EEDO Input enable */
-	reg &= ~(1 << 31);
-	/* Clear Chip Select and all other EEPROM bits */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
-}
-
-
-/******************************************************************************
- * EEPROM read/writes
-******************************************************************************/
-
-#undef EEPROM_DBG
-static int pati_pci_eeprom_erase(void)
-{
-	int i;
-	printf("Erasing EEPROM ");
-	for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) {
-		write_pci_eeprom_offs(i,0xffff);
-		if((i%0x10))
-			printf(".");
-	}
-	printf("\nDone\n");
-	return 0;
-}
-
-static int pati_pci_eeprom_prg(void)
-{
-	int i;
-	i=0;
-	printf("Programming EEPROM ");
-	while(pati_eeprom[i].offset<0xffff) {
-		write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value);
-		#ifdef EEPROM_DBG
-		printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value);
-		#else
-		if((i%0x10))
-			printf(".");
-		#endif
-		i++;
-	}
-	printf("\nDone\n");
-	return 0;
-}
-
-static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size)
-{
-	int i;
-	unsigned short value;
-	unsigned short *buffer =(unsigned short *)addr;
-	if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
-		size = PATI_EEPROM_LAST_OFFSET - offset;
-	}
-	printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2);
-	for( i = offset; i< (offset + size); i+=2) {
-		value = *buffer++;
-		write_pci_eeprom_offs(i,value);
-		#ifdef EEPROM_DBG
-		printf("0x%04X: 0x%04X\n",i, value);
-		#else
-		if((i%0x10))
-			printf(".");
-		#endif
-	}
-	printf("\nDone\n");
-	return 0;
-}
-
-static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size)
-{
-	int i;
-	unsigned short value = 0;
-	unsigned short *buffer =(unsigned short *)addr;
-	if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
-		size = PATI_EEPROM_LAST_OFFSET - offset;
-	}
-	printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2);
-	for( i = offset; i< (offset + size); i+=2) {
-		read_pci_eeprom_offs(i,&value);
-		*buffer++=value;
-		#ifdef EEPROM_DBG
-		printf("0x%04X: 0x%04X\n",i, value);
-		#else
-		if((i%0x10))
-			printf(".");
-		#endif
-	}
-	printf("\nDone\n");
-	return 0;
-}
-
-/******************************************************************************
- * PCI Bridge Registers Dump
-*******************************************************************************/
-static void display_pci_regs(void)
-{
-	printf(" PCI9056_SPACE0_RANGE     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE));
-	printf(" PCI9056_SPACE0_REMAP     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP));
-	printf(" PCI9056_LOCAL_DMA_ARBIT  %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT));
-	printf(" PCI9056_ENDIAN_DESC      %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC));
-	printf(" PCI9056_EXP_ROM_RANGE    %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE));
-	printf(" PCI9056_EXP_ROM_REMAP    %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP));
-	printf(" PCI9056_SPACE0_ROM_DESC  %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC));
-	printf(" PCI9056_DM_RANGE         %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE));
-	printf(" PCI9056_DM_MEM_BASE      %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE));
-	printf(" PCI9056_DM_IO_BASE       %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE));
-	printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP));
-	printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG));
-	printf(" PCI9056_SPACE1_RANGE     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE));
-	printf(" PCI9056_SPACE1_REMAP     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP));
-	printf(" PCI9056_SPACE1_DESC      %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC));
-	printf(" PCI9056_DM_DAC           %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC));
-	printf(" PCI9056_MAILBOX0         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0));
-	printf(" PCI9056_MAILBOX1         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1));
-	printf(" PCI9056_MAILBOX2         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2));
-	printf(" PCI9056_MAILBOX3         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3));
-	printf(" PCI9056_MAILBOX4         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4));
-	printf(" PCI9056_MAILBOX5         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5));
-	printf(" PCI9056_MAILBOX6         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6));
-	printf(" PCI9056_MAILBOX7         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7));
-	printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL));
-	printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL));
-	printf(" PCI9056_INT_CTRL_STAT    %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT));
-	printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT));
-	printf(" PCI9056_PERM_VENDOR_ID   %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID));
-	printf(" PCI9056_REVISION_ID      %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID));
-	printf(" \n");
-	printf(" PCI9056_VENDOR_ID        %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID));
-	printf(" PCI9056_COMMAND          %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND));
-	printf(" PCI9056_REVISION         %08lX\n",PCICFG_GET_REG(PCI9056_REVISION));
-	printf(" PCI9056_CACHE_SIZE       %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE));
-	printf(" PCI9056_RTR_BASE         %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE));
-	printf(" PCI9056_RTR_IO_BASE      %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE));
-	printf(" PCI9056_LOCAL_BASE0      %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0));
-	printf(" PCI9056_LOCAL_BASE1      %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1));
-	printf(" PCI9056_UNUSED_BASE1     %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1));
-	printf(" PCI9056_UNUSED_BASE2     %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2));
-	printf(" PCI9056_CIS_PTR          %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR));
-	printf(" PCI9056_SUB_ID           %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID));
-	printf(" PCI9056_EXP_ROM_BASE     %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE));
-	printf(" PCI9056_CAP_PTR          %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR));
-	printf(" PCI9056_INT_LINE         %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE));
-	printf(" PCI9056_PM_CAP_ID        %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID));
-	printf(" PCI9056_PM_CSR           %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR));
-	printf(" PCI9056_HS_CAP_ID        %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID));
-	printf(" PCI9056_VPD_CAP_ID       %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID));
-	printf(" PCI9056_VPD_DATA         %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA));
-}
-
-
-int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (strcmp(argv[1], "info") == 0)
-	{
-		show_pld_regs();
-		return 0;
-	}
-	if (strcmp(argv[1], "pci") == 0)
-	{
-		display_pci_regs();
-		return 0;
-	}
-	if (strcmp(argv[1], "led") == 0)
-	{
-		int led_nr,led_on;
-		led_nr = (int)simple_strtoul(argv[2], NULL, 10);
-		led_on = (int)simple_strtoul(argv[3], NULL, 10);
-		if(!led_nr)
-			user_led0(led_on);
-		else
-			user_led1(led_on);
-		return 0;
-	}
-#if defined(CONFIG_SYS_PCI_CON_DEVICE)
-	if (strcmp(argv[1], "con") == 0) {
-		pci_con_connect();
-		return 0;
-	}
-	if (strcmp(argv[1], "disc") == 0) {
-		pci_con_disc();
-		return 0;
-	}
-#endif
-	if (strcmp(argv[1], "eeprom") == 0) {
-		unsigned long addr;
-		int size, offset;
-		offset = 0;
-		size = PATI_EEPROM_LAST_OFFSET;
-		if(argc>2) {
-			if(argc>3) {
-				addr = simple_strtoul(argv[3], NULL, 16);
-				if(argc>4)
-					offset = (int) simple_strtoul(argv[4], NULL, 16);
-				if(argc>5)
-					size = (int) simple_strtoul(argv[5], NULL, 16);
-				if (strcmp(argv[2], "read") == 0) {
-					return (pati_pci_eeprom_read(offset, addr, size));
-				}
-				if (strcmp(argv[2], "write") == 0) {
-					return (pati_pci_eeprom_write(offset, addr, size));
-				}
-			}
-			if (strcmp(argv[2], "prg") == 0) {
-				return (pati_pci_eeprom_prg());
-			}
-			if (strcmp(argv[2], "era") == 0) {
-				return (pati_pci_eeprom_erase());
-			}
-			if (strcmp(argv[2], "reload") == 0) {
-				reload_pci_eeprom();
-				return 0;
-			}
-
-
-		}
-	}
-
-	return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-
-U_BOOT_CMD(
-	pati,	8,	1,	do_pati,
-	"PATI specific Cmds",
-	"info - displays board information\n"
-	"pati pci  - displays PCI registers\n"
-	"pati led <nr> <on> \n"
-	"          - switch LED <nr> <on>\n"
-	"pati flash mem [SrcAddr]\n"
-	"          - updates U-Boot with image in memory\n"
-	"pati eeprom <cmd> - PCI EEPROM sub-system\n"
-	"    read <addr> <offset> <size>\n"
-	"          - read PCI EEPROM to <addr> from <offset> <size> words\n"
-	"    write <addr> <offset> <size>\n"
-	"          - write PCI EEPROM from <addr> to <offset> <size> words\n"
-	"    prg   - programm PCI EEPROM with default values\n"
-	"    era   - erase PCI EEPROM (write all word to 0xffff)\n"
-	"    reload- Reload PCI Bridge with EEPROM Values\n"
-	"    NOTE: <addr> must start on word boundary\n"
-	"          <offset> and <size> must be even byte values"
-);
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
deleted file mode 100644
index 1288f74..0000000
--- a/board/mpl/pati/pati.c
+++ /dev/null
@@ -1,610 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
- * Atapted for PATI
- * Denis Peter, d.peter@mpl.ch
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/***********************************************************************************
- * Bits for the SDRAM controller
- * -----------------------------
- *
- * CAL:	CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
- *	the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
- *	controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
- * RCD:	RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
- *	tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
- * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
- *	If set to 1 tWR must be equal or less 50ns.
- * RP:	Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
- *	25ns. If set to 1 tRP must be equal or less 50ns.
- * RC:	Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
- *	or less 75ns. If set to 1 tRC must be equal or less 100ns.
- * LMR:	Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
- *	is the Load Mode Register Command.
- * IIP:	Init in progress. Set to 1 for starting the init sequence
- *	(Precharge All). As long this bit is set, the Precharge All is still in progress.
- *	After command has completed, wait at least for 8 refresh (200usec) before proceed.
- **********************************************************************************/
-
-#include <common.h>
-#include <console.h>
-#include <mpc5xx.h>
-#include <stdio_dev.h>
-#include <pci_ids.h>
-#define PLX9056_LOC
-#include "plx9056.h"
-#include "pati.h"
-
-#if defined(__APPLE__)
-/* Leading underscore on symbols */
-#  define SYM_CHAR "_"
-#else /* No leading character on symbols */
-#  define SYM_CHAR
-#endif
-
-#undef SDRAM_DEBUG
-/*
- * Macros to generate global absolutes.
- */
-#define GEN_SYMNAME(str) SYM_CHAR #str
-#define GEN_VALUE(str) #str
-#define GEN_ABS(name, value) \
-		asm (".globl " GEN_SYMNAME(name)); \
-		asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
-
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/************************************************************************
- * Early debug routines
- */
-void write_hex (unsigned char i)
-{
-	char cc;
-
-	cc = i >> 4;
-	cc &= 0xf;
-	if (cc > 9)
-		serial_putc (cc + 55);
-	else
-		serial_putc (cc + 48);
-	cc = i & 0xf;
-	if (cc > 9)
-		serial_putc (cc + 55);
-	else
-		serial_putc (cc + 48);
-}
-
-#if defined(SDRAM_DEBUG)
-
-void write_4hex (unsigned long val)
-{
-	write_hex ((unsigned char) (val >> 24));
-	write_hex ((unsigned char) (val >> 16));
-	write_hex ((unsigned char) (val >> 8));
-	write_hex ((unsigned char) val);
-}
-
-#endif
-
-unsigned long in32(unsigned long addr)
-{
-	unsigned long *p=(unsigned long *)addr;
-	return *p;
-}
-
-void out32(unsigned long addr,unsigned long data)
-{
-	unsigned long *p=(unsigned long *)addr;
-	*p=data;
-}
-
-typedef struct {
-	unsigned short boardtype; /* Board revision and Population Options */
-	unsigned char cal;		/* cas Latency  0:CAL=2 1:CAL=3 */
-	unsigned char rcd;		/* ras to cas delay  0:<25ns 1:<50ns*/
-	unsigned char wrec;		/* write recovery 0:<25ns 1:<50ns */
-	unsigned char pr;		/* Precharge Command Time 0:<25ns 1:<50ns */
-	unsigned char rc;		/* Auto Refresh to Active Time 0:<75ns 1:<100ns */
-	unsigned char sz;		/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
-} sdram_t;
-
-const sdram_t sdram_table[] = {
-	{ 0x0000,	/* PATI Rev A, 16MByte -1 Board */
-		1,	/* Case Latenty = 3 */
-		0,	/* ras to cas delay  0 (20ns) */
-		0,	/* write recovery 0:<25ns 1:<50ns*/
-		0,	/* Precharge Command Time 0 (20ns) */
-		0,	/* Auto Refresh to Active Time 0 (68) */
-		2	/* log binary => Size 2 = 16MByte, 1=8 */
-	},
-	{ 0xffff, /* terminator */
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff }
-};
-
-
-extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
-
-/*
- * Get RAM size.
- */
-int dram_init(void)
-{
-	unsigned char board_rev;
-	unsigned long reg;
-	unsigned long lmr;
-	int i,timeout;
-
-#if defined(SDRAM_DEBUG)
-	reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
-	puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg));
-	puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg));
-	puts("\nSDRAM  part  0x"); write_4hex(SDRAM_PART(reg));
-	puts(" Vers 0x"); write_4hex(SDRAM_ID(reg));
-	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-	puts("\nBoard rev.   0x"); write_4hex(SYSCNTR_BREV(reg));
-   putc('\n');
-#endif
-	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-	board_rev=(unsigned char)(SYSCNTR_BREV(reg));
-	i=0;
-	while(1) {
-		if(sdram_table[i].boardtype==0xffff) {
-			puts("ERROR, found no table for Board 0x");
-			write_hex(board_rev);
-			while(1);
-		}
-		if(sdram_table[i].boardtype==(unsigned char)board_rev)
-			break;
-		i++;
-	}
-	/* Set CAL, RCD, WREQ, PR and RC Bits */
-#if defined(SDRAM_DEBUG)
-	puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
-#endif
-	/* mask bits */
-	reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) |
-				SET_REG_BIT(1,SDRAM_PR)  |  SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR)  |
-				SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0));
-	/* set bits */
-	reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) |
-			  SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) |
-			  SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) |
-			  SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) |
-			  SET_REG_BIT(sdram_table[i].rc,SDRAM_RC));
-
-	out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
-	/* step 2 set IIP */
-#if defined(SDRAM_DEBUG)
-	puts("step 2 set IIP\n");
-#endif
-	/* step 2 set IIP */
-	reg |= SET_REG_BIT(1,SDRAM_IIP);
-	timeout=0;
-	while (timeout!=0xffff) {
-		__asm__ volatile("eieio");
-		reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-		if((reg & SET_REG_BIT(1,SDRAM_IIP))==0)
-			break;
-		timeout++;
-		udelay(1);
-	}
-	/* wait for at least 8 refresh */
-	udelay(1000);
-	/* set LMR */
-	reg |= SET_REG_BIT(1,SDRAM_LMR);
-	out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
-	__asm__ volatile("eieio");
-	lmr=0x00000002; /* sequential burst 4 data */
-	if(sdram_table[i].cal==1)
-		lmr|=0x00000030; /* cal = 3 */
-	else
-		lmr|=0000000020; /* cal = 2 */
-	/* rest standard operation programmed write burst length */
-	/* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
-	lmr<<=2;
-	in32(CONFIG_SYS_SDRAM_BASE + lmr);
-	/* ok, we're done, set SDRAM size to log2 value of 4MByte*/
-	gd->ram_size = 0x400000 << sdram_table[i].sz;
-
-	return 0;
-}
-
-
-void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp)
-{
-	unsigned long reg;
-	reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE);
-	reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) |
-			   SET_REG_BIT(1,SYSCNTR_FL_VPP) |
-				SET_REG_BIT(1,SYSCNTR_FL_WP));
-
-	reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) |
-			   SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) |
-				SET_REG_BIT(ext_wp,SYSCNTR_FL_WP));
-	out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg);
-	udelay(100);
-}
-
-
-void show_pld_regs(void)
-{
-	unsigned long reg,reg1;
-	reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
-	printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg));
-	printf("SDRAM  part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg));
-	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-	printf("Board rev.  %c\n",(char) (SYSCNTR_BREV(reg)+'A'));
-	printf("Waitstates  %ld\n",GET_SYSCNTR_FLWAIT(reg));
-	printf("SDRAM:      CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n            RC=%ld  LMR=%ld IIP=%ld\n",
-		GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD),
-		GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR),
-		GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR),
-		GET_REG_BIT(reg,SDRAM_IIP));
-	reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1);
-	reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2);
-	printf("HW Config:  FLAG=%ld IP=%ld  index=%ld PRPM=%ld\n            ICW=%ld  ISB=%ld BDIS=%ld  PCIM=%ld\n",
-		GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP),
-		GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM),
-		GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg),
-		GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM));
-	printf("Switches:   MUX=%ld PCI_DIS=%ld Boot_EN=%ld  Config=%ld\n",GET_SDRAM_MUX(reg),
-		GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN),
-		GET_SYSCNTR_CFG(reg1));
-	printf("Misc:       RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
-		GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP),
-		GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP));
-}
-
-
-/****************************************************************
- * Setting IOs
- * -----------
- * GPIO6 is User LED1
- * GPIO7 is Interrupt PLX (Output)
- * GPIO5 is User LED0
- * GPIO2 is PLX USERi (Output)
- * GPIO1 is PLX Interrupt (Input)
- ****************************************************************/
- void init_ios(void)
- {
-	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
-	unsigned long reg;
-	reg=sysconf->sc_sgpiocr; /* Data direction register */
-	reg &= ~0x67000000;
-	reg |= 0x27000000; /* set outpupts */
-	sysconf->sc_sgpiocr=reg; /* Data direction register */
-	reg=sysconf->sc_sgpiodt2; /* Data register */
-	/* set output to 0 */
-	reg &= ~0x27000000;
-	/* set IRQ and USERi to 1 */
-	reg |= 0x28000000;
-	sysconf->sc_sgpiodt2=reg; /* Data register */
-}
-
-void user_led0(int led_on)
-{
-	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
-	unsigned long reg;
-	reg=sysconf->sc_sgpiodt2; /* Data register */
-	if(led_on)	/* set output to 1 */
-		reg |= 0x04000000;
-	else
-		reg &= ~0x04000000;
-	sysconf->sc_sgpiodt2=reg; /* Data register */
-}
-
-void user_led1(int led_on)
-{
-	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
-	unsigned long reg;
-	reg=sysconf->sc_sgpiodt2; /* Data register */
-	if(led_on)	/* set output to 1 */
-		reg |= 0x02000000;
-	else
-		reg &= ~0x02000000;
-	sysconf->sc_sgpiodt2=reg; /* Data register */
-}
-
-int board_early_init_f(void)
-{
-	spi_init_f();
-	return 0;
-}
-
-/****************************************************************
- * Last Stage Init
- ****************************************************************/
-int last_stage_init (void)
-{
-	init_ios();
-	return 0;
-}
-
-/****************************************************************
- * Check the board
- ****************************************************************/
-
-#define BOARD_NAME	"PATI"
-
-int checkboard (void)
-{
-	char s[50];
-	ulong reg;
-	char rev;
-	int i;
-
-	puts ("\nBoard: ");
-	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-	rev=(char)(SYSCNTR_BREV(reg)+'A');
-	i = getenv_f("serial#", s, 32);
-	if ((i == -1)) {
-		puts ("### No HW ID - assuming " BOARD_NAME);
-		printf(" Rev. %c\n",rev);
-	}
-	else {
-		s[sizeof(BOARD_NAME)-1] = 0;
-		printf ("%s-1 Rev %c SN: %s\n", s,rev,
-				&s[sizeof(BOARD_NAME)]);
-	}
-	set_flash_vpp(1,0,0); /* set Flash VPP */
-	return 0;
-}
-
-
-#ifdef CONFIG_SYS_PCI_CON_DEVICE
-/************************************************************************
- * PCI Communication
- *
- * Alive (Pinging):
- * ----------------
- * PCI Host sends message ALIVE, Local acknowledges with ALIVE
- *
- * PCI_CON console over PCI:
- * -------------------------
- * Local side:
- *     - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
- *       data is avaible (PCIMSG_CONN)
- *     - uses PCI9056_MAILBOX1 to send data
- *     - uses PCI9056_MAILBOX0 to receive data
- * PCI side:
- *     - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
- *       data is avaible (PCIMSG_CONN)
- *     - uses PCI9056_MAILBOX0 to send data
- *     - uses PCI9056_MAILBOX1 to receive data
- *
- * How it works:
- *     Send:
- *     - check if PCICON_TRANSMIT_REG is empty
- *     - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
- *     - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
- *       is waiting
- *     Receive:
- *     - get an interrupt via the PCICON_ACK_REG register message
- *       PCIMSG_CONN
- *     - write the data from the PCICON_RECEIVE_REG into the receive
- *       buffer and if the receive buffer is not full, clear the
- *       PCICON_RECEIVE_REG (this allows the counterpart to write more data)
- *     - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
- *
- *     The PCICON_RECEIVE_REG must be cleared by the routine which reads
- *     the receive buffer if the buffer is not full any more
- *
- */
-
-#undef PCI_CON_DEBUG
-
-#ifdef	PCI_CON_DEBUG
-#define	PCI_CON_PRINTF(fmt,args...)	serial_printf (fmt ,##args)
-#else
-#define PCI_CON_PRINTF(fmt,args...)
-#endif
-
-
-/*********************************************************
- * we work only with a receive buffer on eiter side.
- * Transmit buffer is free, if mailbox is cleared.
- * Transmit character is or'ed with 0x80000000
- * PATI receive register MAILBOX0
- * PATI transmit register MAILBOX1
- *********************************************************/
-#define PCICON_RECEIVE_REG	PCI9056_MAILBOX0
-#define PCICON_TRANSMIT_REG	PCI9056_MAILBOX1
-#define PCICON_DBELL_REG	PCI9056_LOC_TO_PCI_DBELL
-#define PCICON_ACK_REG		PCI9056_PCI_TO_LOC_DBELL
-
-
-#define PCIMSG_ALIVE		0x1
-#define PCIMSG_CONN		0x2
-#define PCIMSG_DISC		0x3
-#define PCIMSG_CON_DATA	0x5
-
-
-#define PCICON_GET_REG(x)	(in32(x + PCI_CONFIG_BASE))
-#define PCICON_SET_REG(x,y)	(out32(x + PCI_CONFIG_BASE,y))
-#define PCICON_TX_FLAG		0x80000000
-
-
-#define REC_BUFFER_SIZE	0x100
-int recbuf[REC_BUFFER_SIZE];
-static int r_ptr = 0;
-int w_ptr;
-struct stdio_dev pci_con_dev;
-int conn=0;
-int buff_full=0;
-
-void pci_con_put_it(const char c)
-{
-	/* Test for completition */
-	unsigned long reg;
-	do {
-		reg=PCICON_GET_REG(PCICON_TRANSMIT_REG);
-	}while(reg);
-	reg=PCICON_TX_FLAG + c;
-	PCICON_SET_REG(PCICON_TRANSMIT_REG,reg);
-	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
-}
-
-void pci_con_putc(struct stdio_dev *dev, const char c)
-{
-	pci_con_put_it(c);
-	if(c == '\n')
-		pci_con_put_it('\r');
-}
-
-
-int pci_con_getc(struct stdio_dev *dev)
-{
-	int res;
-	int diff;
-	while(r_ptr==(volatile int)w_ptr);
-	res=recbuf[r_ptr++];
-	if(r_ptr==REC_BUFFER_SIZE)
-		r_ptr=0;
-	if(w_ptr<r_ptr)
-		diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
-	else
-		diff=r_ptr-w_ptr;
-	if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
-		/* clear Mail box */
-			buff_full=0;
-			PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
-	}
-	return res;
-}
-
-int pci_con_tstc(struct stdio_dev *dev)
-{
-	if(r_ptr==(volatile int)w_ptr)
-		return 0;
-	return 1;
-}
-
-void pci_con_puts(struct stdio_dev *dev, const char *s)
-{
-	while (*s) {
-		pci_con_putc(*s);
-		++s;
-	}
-}
-
-void pci_con_init (void)
-{
-	w_ptr = 0;
-	r_ptr = 0;
-	PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
-	conn=1;
-}
-
-/*******************************************
- * IRQ routine
- ******************************************/
-int pci_dorbell_irq(void)
-{
-	unsigned long reg,data;
-	int diff;
-	reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
-	PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg);
-	if(reg & (1<<20) ) {
-		/* read doorbell */
-		reg=PCICON_GET_REG(PCICON_ACK_REG);
-		switch(reg) {
-			case PCIMSG_ALIVE:
-				PCI_CON_PRINTF(" Alive\n");
-				PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE);
-				break;
-			case PCIMSG_CONN:
-				PCI_CON_PRINTF(" Conn %d",conn);
-				w_ptr = 0;
-				r_ptr = 0;
-				buff_full=0;
-				PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
-				conn=1;
-				PCI_CON_PRINTF(" ... %d\n",conn);
-				break;
-			case PCIMSG_CON_DATA:
-				data=PCICON_GET_REG(PCICON_RECEIVE_REG);
-				recbuf[w_ptr++]=(int)(data&0xff);
-				PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)),
-					r_ptr,w_ptr,recbuf[w_ptr-1]);
-				if(w_ptr==REC_BUFFER_SIZE)
-					w_ptr=0;
-				if(w_ptr<r_ptr)
-					diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
-				else
-					diff=r_ptr-w_ptr;
-				if(diff>(REC_BUFFER_SIZE-4))
-					buff_full=1;
-				else
-					/* clear Mail box */
-					PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
-				break;
-			default:
-				serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg);
-		}
-		/* clear IRQ */
-		PCICON_SET_REG(PCICON_ACK_REG,~0L);
-	}
-	return 0;
-}
-
-void pci_con_connect(void)
-{
-	unsigned long reg;
-	conn=0;
-	reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
-	/* default 0x0f010180 */
-	reg &= 0xff000000;
-	reg |= 0x00030000; /* enable local dorbell */
-	reg |= 0x00000300; /* enable PCI dorbell */
-	PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg);
-	irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL);
-	memset (&pci_con_dev, 0, sizeof (pci_con_dev));
-	strcpy (pci_con_dev.name, "pci_con");
-	pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
-	pci_con_dev.putc = pci_con_putc;
-	pci_con_dev.puts = pci_con_puts;
-	pci_con_dev.getc = pci_con_getc;
-	pci_con_dev.tstc = pci_con_tstc;
-	stdio_register (&pci_con_dev);
-	printf("PATI ready for PCI connection, type ctrl-c for exit\n");
-	do {
-		udelay(10);
-		if((volatile int)conn)
-			break;
-		if(ctrlc()) {
-			irq_free_handler(0x2);
-			return;
-		}
-	}while(1);
-	console_assign(stdin,"pci_con");
-	console_assign(stderr,"pci_con");
-	console_assign(stdout,"pci_con");
-}
-
-void pci_con_disc(void)
-{
-	console_assign(stdin,"serial");
-	console_assign(stderr,"serial");
-	console_assign(stdout,"serial");
-	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC);
-	/* reconnection */
-	irq_free_handler(0x02);
-	pci_con_connect();
-}
-#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
-
-/*
- * Absolute environment address for linker file.
- */
-GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
deleted file mode 100644
index 93a5918..0000000
--- a/board/mpl/pati/pati.h
+++ /dev/null
@@ -1,423 +0,0 @@
-/*
- * (C) Copyright 2003
- * Denis Peter, d.peter@mpl.ch
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/************************************************************************
- * MACROS and register definitions for PATI Registers
- ************************************************************************/
-#ifndef __PATI_H_
-#define __PATI_H_	1
-
-#define PLD_PART_ID		0x0
-#define PLD_BOARD_TIMING	0x4
-#define PLD_CONF_REG1		0x8
-#define PLD_CONF_REG2		0xC
-#define PLD_CONF_RES		0x10
-
-#define SET_REG_BIT(y,x) (y<<(31-x))
-#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
-
-/* SDRAM Controller PLD_PART_ID */
-/* 9  10 11 12 13 14 19 31 */
-#define SDRAM_PART3	9
-#define SDRAM_PART2	10
-#define SDRAM_PART1	11
-#define SDRAM_PART0	12
-#define SDRAM_ID3	13
-#define SDRAM_ID2	14
-#define SDRAM_ID1	19
-#define SDRAM_ID0	31
-
-#define SDRAM_PART(x)	(	\
-	(GET_REG_BIT(x,SDRAM_PART3)<<3) |\
-	(GET_REG_BIT(x,SDRAM_PART2)<<2) |\
-	(GET_REG_BIT(x,SDRAM_PART1)<<1) |\
-	(GET_REG_BIT(x,SDRAM_PART0)))
-
-#define SDRAM_ID(x)	(	\
-	(GET_REG_BIT(x,SDRAM_ID3)<<3) |\
-	(GET_REG_BIT(x,SDRAM_ID2)<<2) |\
-	(GET_REG_BIT(x,SDRAM_ID1)<<1) |\
-	(GET_REG_BIT(x,SDRAM_ID0)))
-
-/* System Controller */
-/* 0  1 3 4 5 16 20 28 29 30 */
-#define SYSCNTR_PART4	0
-#define SYSCNTR_PART3	1
-#define SYSCNTR_PART2	3
-#define SYSCNTR_PART1	4
-#define SYSCNTR_PART0	5
-#define SYSCNTR_ID4	16
-#define SYSCNTR_ID3	20
-#define SYSCNTR_ID2	28
-#define SYSCNTR_ID1	29
-#define SYSCNTR_ID0	30
-
-#define SYSCNTR_PART(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
-	(GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
-	(GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_PART0)))
-
-#define SYSCNTR_ID(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
-	(GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
-	(GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_ID0)))
-
-/* SDRAM Controller PLD_BOARD_TIMING */
-/* 9  10 11 12 13 14 19 31 */
-#define SDRAM_CAL	9
-#define SDRAM_RCD	10
-#define SDRAM_WREQ	11
-#define SDRAM_PR	12
-#define SDRAM_RC	13
-#define SDRAM_LMR	14
-#define SDRAM_IIP	19
-#define SDRAM_RES0	31
-/* System Controller */
-/* 0  1 3 4 5 16 20 28 29 30 */
-#define SYSCNTR_BREV0	0
-#define SYSCNTR_BREV1	1
-#define SYSCNTR_BREV2	3
-#define SYSCNTR_BREV3	4
-#define SYSCNTR_RES0	5
-#define SYSCNTR_RES1	16
-#define SYSCNTR_RES2	20
-#define SYSCNTR_FLWAIT2	28
-#define SYSCNTR_FLWAIT1	29
-#define SYSCNTR_FLWAIT0	30
-
-#define SYSCNTR_BREV(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
-	(GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_BREV0)))
-
-#define GET_SYSCNTR_FLWAIT(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
-
-#define SET_SYSCNTR_FLWAIT(x)	(	\
-	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
-	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
-	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
-
-/* SDRAM Controller REG 2*/
-/* 9  10 11 12 13 14 19 31 */
-#define SDRAM_MUX0	9
-#define SDRAM_MUX1	10
-#define SDRAM_PDIS	11
-#define SDRAM_RES1	12
-#define SDRAM_RES2	13
-#define SDRAM_RES3	14
-#define SDRAM_RES4	19
-#define SDRAM_RIP	31
-
-#define GET_SDRAM_MUX(x)	(	\
-	(GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
-	(GET_REG_BIT(x,SDRAM_MUX0)))
-
-
-/* System Controller */
-/* 0  1 3 4 5 16 20 28 29 30 */
-#define SYSCNTR_FLAG	0
-#define SYSCNTR_IP	1
-#define SYSCNTR_BIND2	3
-#define SYSCNTR_BIND1	4
-#define SYSCNTR_BIND0	5
-#define SYSCNTR_PRM	16
-#define SYSCNTR_ICW	20
-#define SYSCNTR_ISB2	28
-#define SYSCNTR_ISB1	29
-#define SYSCNTR_ISB0	30
-
-#define GET_SYSCNTR_BOOTIND(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_BIND0)))
-
-#define SET_SYSCNTR_BOOTIND(x)	(	\
-	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
-	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
-	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
-
-#define GET_SYSCNTR_ISB(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
-	(GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
-	(GET_REG_BIT(x,SYSCNTR_ISB0)))
-
-#define SET_SYSCNTR_ISB(x)	(	\
-	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
-	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
-	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
-
-/* SDRAM Controller REG 3*/
-/* 9  10 11 12 13 14 19 31 */
-#define SDRAM_RES5	9
-#define SDRAM_CFG1	10
-#define SDRAM_CFG2	11
-#define SDRAM_CFG3	12
-#define SDRAM_RES6	13
-#define SDRAM_CFG5	14
-#define SDRAM_CFG6	19
-#define SDRAM_RES7	31
-
-#define GET_SDRAM_CFG(x)	(	\
-	(GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
-	(GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
-	(GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
-	(GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
-	(GET_REG_BIT(x,SDRAM_CFG1)))
-
-/* System Controller */
-/* 0  1 3 4 5 16 20 28 29 30 */
-#define SYSCNTR_BDIS	0
-#define SYSCNTR_PCIM	1
-#define SYSCNTR_CFG0	3
-#define SYSCNTR_CFG1	4
-#define SYSCNTR_CFG2	5
-#define SYSCNTR_CFG3	16
-#define SYSCNTR_BOOTEN	20
-#define SYSCNTR_CPU_VPP	28
-#define SYSCNTR_FL_VPP	29
-#define SYSCNTR_FL_WP	30
-
-#define GET_SYSCNTR_CFG(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
-	(GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
-	(GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
-	(GET_REG_BIT(x,SYSCNTR_CFG0)))
-
-
-/***************************************************************
- * MISC Defines
- ***************************************************************/
-
-#define PCI_VENDOR_ID_MPL	0x18E6
-#define PCI_DEVICE_ID_PATI	0x00DA
-
-#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
-#define PATI_FIRMWARE_START_OFFSET	0x00300000
-#endif
-
-#define PATI_ENDIAN_MODE	0x3E
-
-/*******************************************
- * PATI Mapping:
- * -------------
- * PCI Map:
- * -------
- * All addreses are mapped into the memory area
- * (IO Area on some areas may also be possible)
- * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
- * - pci_space0_addr:  configurable
- * - pci_space1_addr	  configurable
- *
- * Local Map:
- * ----------
- * Local addresses (Remap)
- * - SDRAM      0x06000000 Size 16MByte mask 0xff000000
- * - EPLD CFG   0x07000000 Size 512Bytes
- * - FLASH      0x03000000 Size up to 8MByte
- * - CPU        0x01000000 Size 4MByte (only accessable if special configured)
- *
- * Implemention:
- * -------------
- * To prevent using large resources reservation on the host following
- * PCI mapping is choosed:
- * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
- * - pci_space0_addr:  configured to the EPLD Config Area size 256Bytes
- * - pci_space1_addr:  configured to the SDRAM Area size 1MBytes, this
- *                     space is used to switch between SDRAM, Flash and CPU
- *
- */
-
-/* Attribute definitions */
-#define PATI_BUS_SIZE_8		0
-#define PATI_BUS_SIZE_16	1
-#define PATI_BUS_SIZE_32	3
-
-#define PATI_SPACE0_MASK	(0xFEFFFE00)  /* Mask Attributes */
-#define PATI_SPACE1_MASK	(0x00000000)  /* Mask Attributes */
-
-#define PATI_EXTRA_LONG_EEPROM	1
-
-#define SPACE0_TA_ENABLE (1<<6)
-#define SPACE1_TA_ENABLE (1<<6)
-
-/* Config Area */
-#define PATI_LOC_CFG_ADDR		0x07000000		/* Local Address */
-#define PATI_LOC_CFG_MASK		0xFFFFFF00		/* 256 Bytes */
-/* Attributes */
-#define PATI_LOC_CFG_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
-#define PATI_LOC_CFG_BURST		0			/* No Burst */
-#define PATI_LOC_CFG_NO_PREFETCH	1			/* No Prefetch */
-#define PATI_LOC_CFG_TA_ENABLE		1			/* Enable TA */
-
-#define PATI_LOC_CFG_SPACE0_ATTR  ( \
-		PATI_LOC_CFG_BUS_SIZE | \
-		(PATI_LOC_CFG_TA_ENABLE << 6) | \
-		(PATI_LOC_CFG_NO_PREFETCH << 8) | \
-		(PATI_LOC_CFG_BURST << 24) | \
-		(PATI_EXTRA_LONG_EEPROM << 25))
-
-/* should never be used */
-#define PATI_LOC_CFG_SPACE1_ATTR  ( \
-		PATI_LOC_CFG_BUS_SIZE | \
-		(PATI_LOC_CFG_TA_ENABLE << 6) | \
-		(PATI_LOC_CFG_NO_PREFETCH << 9) | \
-		(PATI_LOC_CFG_BURST << 8))
-
-
-/* SDRAM Area */
-#define PATI_LOC_SDRAM_ADDR		0x06000000		/* Local Address */
-#define PATI_LOC_SDRAM_MASK		0xFFF00000		/* 1MByte */
-/* Attributes */
-#define PATI_LOC_SDRAM_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
-#define PATI_LOC_SDRAM_BURST		0			/* No Burst */
-#define PATI_LOC_SDRAM_NO_PREFETCH	0			/* Prefetch */
-#define PATI_LOC_SDRAM_TA_ENABLE	1			/* Enable TA */
-
-/* should never be used */
-#define PATI_LOC_SDRAM_SPACE0_ATTR  ( \
-		PATI_LOC_SDRAM_BUS_SIZE | \
-		(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
-		(PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
-		(PATI_LOC_SDRAM_BURST << 24) | \
-		(PATI_EXTRA_LONG_EEPROM << 25))
-
-#define PATI_LOC_SDRAM_SPACE1_ATTR  ( \
-		PATI_LOC_SDRAM_BUS_SIZE | \
-		(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
-		(PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
-		(PATI_LOC_SDRAM_BURST << 8))
-
-
-/* Flash Area */
-#define PATI_LOC_FLASH_ADDR		0x03000000		/* Local Address */
-#define PATI_LOC_FLASH_MASK		0xFFF00000		/* 1MByte */
-/* Attributes */
-#define PATI_LOC_FLASH_BUS_SIZE		PATI_BUS_SIZE_16	/* 16 Bit */
-#define PATI_LOC_FLASH_BURST		0			/* No Burst */
-#define PATI_LOC_FLASH_NO_PREFETCH	1			/* No Prefetch */
-#define PATI_LOC_FLASH_TA_ENABLE	1			/* Enable TA */
-
-/* should never be used */
-#define PATI_LOC_FLASH_SPACE0_ATTR  ( \
-		PATI_LOC_FLASH_BUS_SIZE | \
-		(PATI_LOC_FLASH_TA_ENABLE << 6) | \
-		(PATI_LOC_FLASH_NO_PREFETCH << 8) | \
-		(PATI_LOC_FLASH_BURST << 24) | \
-		(PATI_EXTRA_LONG_EEPROM << 25))
-
-#define PATI_LOC_FLASH_SPACE1_ATTR  ( \
-		PATI_LOC_FLASH_BUS_SIZE | \
-		(PATI_LOC_FLASH_TA_ENABLE << 6) | \
-		(PATI_LOC_FLASH_NO_PREFETCH << 9) | \
-		(PATI_LOC_FLASH_BURST << 8))
-
-
-/* CPU Area */
-#define PATI_LOC_CPU_ADDR		0x01000000		/* Local Address */
-#define PATI_LOC_CPU_MASK		0xFFF00000		/* 1Mbyte */
-/* Attributes */
-#define PATI_LOC_CPU_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
-#define PATI_LOC_CPU_BURST		0			/* No Burst */
-#define PATI_LOC_CPU_NO_PREFETCH	1			/* No Prefetch */
-#define PATI_LOC_CPU_TA_ENABLE		1			/* Enable TA */
-
-/* should never be used */
-#define PATI_LOC_CPU_SPACE0_ATTR  ( \
-		PATI_LOC_CPU_BUS_SIZE | \
-		(PATI_LOC_CPU_TA_ENABLE << 6) | \
-		(PATI_LOC_CPU_NO_PREFETCH << 8) | \
-		(PATI_LOC_CPU_BURST << 24) | \
-		(PATI_EXTRA_CPU_EEPROM << 25))
-
-#define PATI_LOC_CPU_SPACE1_ATTR  ( \
-		PATI_LOC_CPU_BUS_SIZE | \
-		(PATI_LOC_CPU_TA_ENABLE << 6) | \
-		(PATI_LOC_CPU_NO_PREFETCH << 9) | \
-		(PATI_LOC_CPU_BURST << 8))
-
-/***************************************************
- * Hardware Config word definition
- ***************************************************/
-#define BOOT_EXT_FLASH		0x00000000
-#define BOOT_INT_FLASH		0x00000004
-#define BOOT_FROM_PCI		0x00000006
-#define BOOT_FROM_SDRAM		0x00000005
-
-#define ENABLE_INT_ARB		0x00000008
-
-#define INITIAL_IRQ_PREF	0x00000010
-
-#define INITIAL_MEM_0M		0x00000000
-#define INITIAL_MEM_4M		0x00000080
-#define INITIAL_MEM_8M		0x00000040
-#define INITIAL_MEM_12M		0x000000C0
-#define INITIAL_MEM_16M		0x00000020
-#define INITIAL_MEM_20M		0x000000A0
-#define INITIAL_MEM_24M		0x00000060
-#define INITIAL_MEM_28M		0x000000E0
-/* CONF */
-#define INTERNAL_HWCONF		0x00000100
-/* PRPM */
-#define LOCAL_CPU_SLAVE		0x00000200
-/* BDIS */
-#define DISABLE_MEM_CNTR	0x00000400
-/* PCIM */
-#define PCI_MASTER_ONLY		0x00000800
-
-
-#define PATI_HW_START		((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
-#define PATI_HW_PCI_ONLY	((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
-#define PATI_HW_CPU_ACC		((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
-#define PATI_HW_CPU_SLAVE	((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
-
-/***************************************************
- * Direct Master Config
- ***************************************************/
-#define PATI_DMASTER_PCI_ADDR		0x01000000
-#define PATI_BUS_MASTER 1
-
-
-#define PATI_DMASTER_MASK		0xFFF00000  /* 1MByte */
-#define PATI_DMASTER_ADDR		0x01000000  /* Local Address */
-
-#define PATI_DMASTER_MEMORY_EN		0x00000001 /* 0x00000001 */
-#define PATI_DMASTER_READ_AHEAD		0x00000004 /* 0x00000004 */
-#define PATI_DMASTER_READ_NOT_AHEAD	0x00000000 /* 0x00000004 */
-#define PATI_DMASTER_PRE_SIZE_CNTRL_0	0x00000000
-#define PATI_DMASTER_PRE_SIZE_CNTRL_4	0x00000008
-#define PATI_DMASTER_PRE_SIZE_CNTRL_8	0x00001000
-#define PATI_DMASTER_PRE_SIZE_CNTRL_16	0x00001008
-#define PATI_DMASTER_REL_PCI		0x00000000
-#define PATI_DMASTER_NOT_REL_PCI	0x00000010
-#define PATI_DMASTER_WR_INVAL		0x00000200
-#define PATI_DMASTER_NOT_WR_INVAL	0x00000000
-#define PATI_DMASTER_PRE_LIMIT		0x00000800
-#define PATI_DMASTER_PRE_CONT		0x00000000
-#define PATI_DMASTER_DELAY_WR_0		0x00000000
-#define PATI_DMASTER_DELAY_WR_4		0x00004000
-#define PATI_DMASTER_DELAY_WR_8		0x00008000
-#define PATI_DMASTER_DELAY_WR_16	0x0000C000
-
-#define PATI_DMASTER_PCI_ADDR_MASK	0xFFFF0000
-
-#define PATI_DMASTER_ATTR	\
-	PATI_DMASTER_MEMORY_EN | \
-	PATI_DMASTER_READ_AHEAD | \
-	PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
-	PATI_DMASTER_REL_PCI | \
-	PATI_DMASTER_NOT_WR_INVAL | \
-	PATI_DMASTER_PRE_LIMIT | \
-	PATI_DMASTER_DELAY_WR_0
-
-
-#endif /* #ifndef __PATI_H_ */
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
deleted file mode 100644
index 459c143..0000000
--- a/board/mpl/pati/pci_eeprom.h
+++ /dev/null
@@ -1,90 +0,0 @@
-#ifndef __PCI_EEPROM_H_
-#define __PCI_EEPROM_H_	1
-
-#include "pati.h"
-/******************************************************************************
- * Eeprom Support
- ******************************************************************************/
-/**********************************************
-*               Definitions
-**********************************************/
-#define EE46_CMD_LEN    9       /* Bits in instructions */
-#define EE56_CMD_LEN    11      /* Bits in instructions */
-#define EE66_CMD_LEN    11      /* Bits in instructions */
-#define EE_READ         0x0180  /* 01 1000 0000 read instruction */
-#define EE_WRITE        0x0140  /* 01 0100 0000 write instruction */
-#define EE_WREN         0x0130  /* 01 0011 0000 write enable instruction */
-#define EE_WRALL        0x0110  /* 01 0001 0000 write all registers */
-#define EE_PRREAD       0x0180  /* 01 1000 0000 read address stored in Protect Register */
-#define EE_PRWRITE      0x0140  /* 01 0100 0000 write the address into PR */
-#define EE_WDS          0x0100  /* 01 0000 0000 write disable instruction */
-#define EE_PREN         0x0130  /* 01 0011 0000 protect enable instruction */
-#define EE_PRCLEAR      0x01FF  /* 01 1111 1111 clear protect register instr */
-#define EE_PRDS         0x0100  /* 01 0000 0000 ONE TIME ONLY, permenant */
-
-/***************************************************
- * EEPROM
- ***************************************************/
-#define LOW_WORD(x)	(((x) & 0xFFFF))
-#define HIGH_WORD(x)	(((x) >> 16) & 0xFFFF)
-
-typedef struct pci_eeprom_t {
-	unsigned short offset;
-	unsigned short value;
-} pci_eeprom;
-
-static pci_eeprom pati_eeprom[] = {
-	{ 0x00,PCI_DEVICE_ID_PATI },	/* PCI Device ID PCIIDR[31:16] */
-	{ 0x02,PCI_VENDOR_ID_MPL },	/* PCI Vendor ID PCIIDR[15:0] */
-	{ 0x04,PCI_CLASS_PROCESSOR_POWERPC },	/* PCI Class Code PCICCR[23:8] */
-	{ 0x06,0x00BA },	/* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
-	{ 0x08,0x0007 },	/* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
-	{ 0x0A,0x0100 },	/* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
-	{ 0x0C,0x0000 },	/* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
-	{ 0x0E,0x0000 },	/* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
-	{ 0x10,0x0000 },	/* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
-	{ 0x12,0x0000 },	/* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
-	{ 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) },	/* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
-	{ 0x16,LOW_WORD(PATI_LOC_CFG_MASK) },	/* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
-	{ 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) },	/* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
-	{ 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 },	/* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
-	{ 0x1C,0x0000 },	/* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
-	{ 0x1E,0x0000 },	/* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
-	{ 0x20,0x0030 },	/* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
-	{ 0x22,0x0510 },	/* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
-	{ 0x24,0x0000 },	/* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
-	{ 0x26,0x0000 },	/* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
-	{ 0x28,0x0000 },	/* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
-	{ 0x2A,0x0000 },	/* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
-	{ 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) },	/* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
-	{ 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) },	/* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
-	{ 0x30,HIGH_WORD(PATI_DMASTER_MASK) },	/* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
-	{ 0x32,LOW_WORD(PATI_DMASTER_MASK) },	/* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
-	{ 0x34,HIGH_WORD(PATI_DMASTER_ADDR) },	/* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
-	{ 0x36,LOW_WORD(PATI_DMASTER_ADDR) },	/* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
-	{ 0x38,0x0000 },	/* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
-	{ 0x3A,0x0000 },	/* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
-	{ 0x3C,0x0000 },	/* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
-	{ 0x3E,0x0000 },	/* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
-	{ 0x40,0x0000 },	/* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
-	{ 0x42,0x0000 },	/* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
-	{ 0x44,0x0000 },	/* PCI Subsystem ID PCISID[15:0] */
-	{ 0x46,0x0000 },	/* PCI Subsystem Vendor ID PCISVID[15:0] */
-	{ 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) },	/* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
-	{ 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) },	/* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
-	{ 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) },	/* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
-	{ 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 },	/* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
-	{ 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
-	{ 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
-	{ 0x54,0x0000 },	/* Hot Swap Control/Status (Reserved) Reserved */
-	{ 0x56,0x0000 },	/* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
-	{ 0x58,0x0000 },	/* Reserved Reserved */
-	{ 0x5A,0x0000 },	/* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
-	{ 0x5C,0x0000 },	/* Power Management Capabilities PMC[15:9, 2:0] */
-	{ 0x5E,0x0000 },	/* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
-	{ 0x60,0x0000 },	/* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
-	{ 0x62,0x0000 },	/* Power Management Control/Status PMCSR[14:8] */
-	{ 0xFFFF,0xFFFF}	/* terminaror */
-};
-#define PATI_EEPROM_LAST_OFFSET	0x64
-#endif /* #ifndef __PCI_EEPROM_H_ */
diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h
deleted file mode 100644
index 754e720..0000000
--- a/board/mpl/pati/plx9056.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2003
- * Denis Peter, d.peter@mpl.ch
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/* PLX9096 register definitions
-*/
-#ifndef __PLX9056_H_
-#define __PLX9056_H_	1
-
-#include <pci.h>
-
-#ifdef PLX9056_LOC
-#define LOCAL_OFFSET					0x080
-/* PCI Config regs */
-#else
-#define LOCAL_OFFSET					0x000
-#endif
-
-#define PCI9056_VENDOR_ID            PCI_VENDOR_ID
-/*#define PCI9656_DEVICE_ID            PCI_DEVICE_ID */
-#define PCI9056_COMMAND              PCI_COMMAND
-/*#define PCI9656_STATUS               PCI_STATUS */
-#define PCI9056_REVISION             PCI_REVISION_ID
-
-#define PCI9056_CACHE_SIZE           PCI_CACHE_LINE_SIZE
-#define PCI9056_RTR_BASE             PCI_BASE_ADDRESS_0
-#define PCI9056_RTR_IO_BASE          PCI_BASE_ADDRESS_1
-#define PCI9056_LOCAL_BASE0          PCI_BASE_ADDRESS_2
-#define PCI9056_LOCAL_BASE1          PCI_BASE_ADDRESS_3
-#define PCI9056_UNUSED_BASE1         PCI_BASE_ADDRESS_4
-#define PCI9056_UNUSED_BASE2         PCI_BASE_ADDRESS_5
-#define PCI9056_CIS_PTR              PCI_CARDBUS_CIS
-#define PCI9056_SUB_ID               PCI_SUBSYSTEM_VENDOR_ID
-#define PCI9056_EXP_ROM_BASE         PCI_ROM_ADDRESS
-#define PCI9056_CAP_PTR              PCI_CAPABILITY_LIST
-#define PCI9056_INT_LINE             PCI_INTERRUPT_LINE
-
-#if defined(PLX9056_LOC)
-    #define PCI9056_PM_CAP_ID            0x180
-    #define PCI9056_PM_CSR               0x184
-    #define PCI9056_HS_CAP_ID            0x188
-    #define PCI9056_VPD_CAP_ID           0x18C
-    #define PCI9056_VPD_DATA             0x190
-#endif
-
-
-#define PCI_DEVICE_ID_PLX9056		0x9056
-
-/* Local Configuration Registers Accessible via the PCI Base address + Variable */
-#define PCI9056_SPACE0_RANGE         (0x000 + LOCAL_OFFSET)
-#define PCI9056_SPACE0_REMAP         (0x004 + LOCAL_OFFSET)
-#define PCI9056_LOCAL_DMA_ARBIT      (0x008 + LOCAL_OFFSET)
-#define PCI9056_ENDIAN_DESC          (0x00c + LOCAL_OFFSET)
-#define PCI9056_EXP_ROM_RANGE        (0x010 + LOCAL_OFFSET)
-#define PCI9056_EXP_ROM_REMAP        (0x014 + LOCAL_OFFSET)
-#define PCI9056_SPACE0_ROM_DESC      (0x018 + LOCAL_OFFSET)
-#define PCI9056_DM_RANGE             (0x01c + LOCAL_OFFSET)
-#define PCI9056_DM_MEM_BASE          (0x020 + LOCAL_OFFSET)
-#define PCI9056_DM_IO_BASE           (0x024 + LOCAL_OFFSET)
-#define PCI9056_DM_PCI_MEM_REMAP     (0x028 + LOCAL_OFFSET)
-#define PCI9056_DM_PCI_IO_CONFIG     (0x02c + LOCAL_OFFSET)
-#define PCI9056_SPACE1_RANGE         (0x0f0 + LOCAL_OFFSET)
-#define PCI9056_SPACE1_REMAP         (0x0f4 + LOCAL_OFFSET)
-#define PCI9056_SPACE1_DESC          (0x0f8 + LOCAL_OFFSET)
-#define PCI9056_DM_DAC               (0x0fc + LOCAL_OFFSET)
-
-#ifdef PLX9056_LOC
-#define PCI9056_ARBITER_CTRL         0x1A0
-#define PCI9056_ABORT_ADDRESS        0x1A4
-#endif
-
-/* Runtime registers  PCI Address + LOCAL_OFFSET */
-#ifdef PLX9056_LOC
-#define PCI9056_MAILBOX0				0x0C0
-#define PCI9056_MAILBOX1				0x0C4
-#else
-#define PCI9056_MAILBOX0				0x078
-#define PCI9056_MAILBOX1				0x07c
-#endif
-
-#define PCI9056_MAILBOX2				(0x048 + LOCAL_OFFSET)
-#define PCI9056_MAILBOX3				(0x04c + LOCAL_OFFSET)
-#define PCI9056_MAILBOX4				(0x050 + LOCAL_OFFSET)
-#define PCI9056_MAILBOX5				(0x054 + LOCAL_OFFSET)
-#define PCI9056_MAILBOX6				(0x058 + LOCAL_OFFSET)
-#define PCI9056_MAILBOX7				(0x05c + LOCAL_OFFSET)
-#define PCI9056_PCI_TO_LOC_DBELL		(0x060 + LOCAL_OFFSET)
-#define PCI9056_LOC_TO_PCI_DBELL		(0x064 + LOCAL_OFFSET)
-#define PCI9056_INT_CTRL_STAT			(0x068 + LOCAL_OFFSET)
-#define PCI9056_EEPROM_CTRL_STAT		(0x06c + LOCAL_OFFSET)
-#define PCI9056_PERM_VENDOR_ID		(0x070 + LOCAL_OFFSET)
-#define PCI9056_REVISION_ID			(0x074 + LOCAL_OFFSET)
-
-#endif /* #ifndef __PLX9056_H_ */