Merge branch 'next'

157 files changed, 3730 insertions, 3612 deletions

diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 91eec35..36b67f0 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -27,6 +27,10 @@ config SPL_TEXT_BASE
 config SPL_OPENSBI_LOAD_ADDR
 	default 0x01000000
 
+config SYS_FDT_BASE
+	hex
+	default 0x800f0000 if OF_SEPARATE
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select RISCV_NDS
diff --git a/board/advantech/imx8mp_rsb3720a1/Kconfig b/board/advantech/imx8mp_rsb3720a1/Kconfig
index 4486ed6..95cac7c 100644
--- a/board/advantech/imx8mp_rsb3720a1/Kconfig
+++ b/board/advantech/imx8mp_rsb3720a1/Kconfig
@@ -9,6 +9,4 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "imx8mp_rsb3720"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index f129ebd..0a1b2c9 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -28,12 +28,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
-	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
 #ifdef CONFIG_NAND_MXS
 static void setup_gpmi_nand(void)
 {
@@ -69,12 +63,6 @@ u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 
 int board_early_init_f(void)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
 	init_uart_clk(2);
 
 	return 0;
diff --git a/board/advantech/imx8qm_rom7720_a1/Kconfig b/board/advantech/imx8qm_rom7720_a1/Kconfig
index 8bf3a7d..c846537 100644
--- a/board/advantech/imx8qm_rom7720_a1/Kconfig
+++ b/board/advantech/imx8qm_rom7720_a1/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/advantech/imx8qm_rom7720_a1/imximage.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/armadeus/opos6uldev/opos6uldev.env b/board/armadeus/opos6uldev/opos6uldev.env
new file mode 100644
index 0000000..585f28c
--- /dev/null
+++ b/board/armadeus/opos6uldev/opos6uldev.env
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Copyright (C) 2017 Armadeus Systems
+ */
+
+/* Environment is stored in the eMMC boot partition */
+
+env_version=100
+consoledev=ttymxc0
+board_name=opos6ul
+fdt_addr=0x88000000
+fdt_high=0xffffffff
+fdt_name=opos6uldev
+initrd_high=0xffffffff
+ip_dyn=yes
+stdin=serial
+stdout=serial
+stderr=serial
+mmcdev=0
+mmcpart=2
+mmcroot=/dev/mmcblk0p2 ro
+mmcrootfstype=ext4 rootwait
+kernelimg=opos6ul-linux.bin
+splashpos=0,0
+splashimage=CONFIG_SYS_LOAD_ADDR
+videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0
+check_env=if test -n ${flash_env_version};
+	then env default env_version;
+	else env set flash_env_version ${env_version}; env save;
+	fi;
+	if itest ${flash_env_version} != ${env_version}; then
+		echo "*** Warning - Environment version
+		 change suggests: run flash_reset_env; reset";
+		env default flash_reset_env;
+	else exit; fi; 
+flash_reset_env=env default -f -a && saveenv &&
+	echo Environment variables erased!
+download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl
+flash_uboot_spl=
+	if mmc dev 0 1; then
+		setexpr sz ${filesize} / 0x200;
+		setexpr sz ${sz} + 1;
+		if mmc write ${loadaddr} 0x2 ${sz}; then
+			echo Flashing of U-boot SPL succeed;
+		else echo Flashing of U-boot SPL failed;
+		fi;
+	fi;
+download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img
+flash_uboot_img=
+	if mmc dev 0 1; then
+		setexpr sz ${filesize} / 0x200;
+		setexpr sz ${sz} + 1;
+		if mmc write ${loadaddr} 0x8a ${sz}; then
+			echo Flashing of U-boot image succeed;
+		else echo Flashing of U-boot image failed;
+		fi;
+	fi;
+update_uboot=run download_uboot_spl flash_uboot_spl
+	download_uboot_img flash_uboot_img
+download_kernel=tftpboot ${loadaddr} ${kernelimg}
+flash_kernel=
+	if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then
+		echo kernel update succeed;
+		else echo kernel update failed;
+	fi;
+update_kernel=run download_kernel flash_kernel
+download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb
+flash_dtb=
+	if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then
+		echo dtb update succeed;
+		else echo dtb update in failed;
+	fi;
+update_dtb=run download_dtb flash_dtb
+download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4
+flash_rootfs=
+	if mmc dev 0 0; then
+		setexpr nbblocks ${filesize} / 0x200;
+		setexpr nbblocks ${nbblocks} + 1;
+		if mmc write ${loadaddr} 0x40800 ${nbblocks}; then
+			echo Flashing of rootfs image succeed;
+		else echo Flashing of rootfs image failed;
+		fi;
+	fi;
+update_rootfs=run download_rootfs flash_rootfs
+flash_failsafe=
+	if mmc dev 0 0; then
+		setexpr nbblocks ${filesize} / 0x200;
+		setexpr nbblocks ${nbblocks} + 1;
+		if mmc write ${loadaddr} 0x800 ${nbblocks}; then
+			echo Flashing of rootfs image in failsafe partition succeed;
+		else echo Flashing of rootfs image in failsafe partition failed;
+		fi;
+	fi;
+update_failsafe=run download_rootfs flash_failsafe
+download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4
+flash_userdata=
+	if mmc dev 0 0; then
+		setexpr nbblocks ${filesize} / 0x200;
+		setexpr nbblocks ${nbblocks} + 1;
+		if mmc write ${loadaddr} 0 ${nbblocks}; then
+			echo Flashing of user_data image succeed;
+		else echo Flashing of user_data image failed;
+		fi;
+	fi;
+update_userdata=run download_userdata flash_userdata; mmc rescan
+erase_userdata=
+	if mmc dev 0 0; then
+		echo Erasing eMMC User Data partition, no way out...;
+		mw ${loadaddr} 0 0x200000;
+		mmc write ${loadaddr} 0 0x1000;
+		mmc write ${loadaddr} 0x800 0x1000;
+		mmc write ${loadaddr} 0x40800 0x1000;
+		mmc write ${loadaddr} 0x440800 0x1000;
+	fi;
+	mmc rescan
+update_all=run update_rootfs update_uboot
+initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}
+addipargs=setenv bootargs ${bootargs}
+	ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
+addmmcargs=setenv bootargs ${bootargs} root=${mmcroot}
+	rootfstype=${mmcrootfstype}
+emmcboot=run initargs; run addmmcargs;
+	load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} &&
+	load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb &&
+	bootz ${loadaddr} - ${fdt_addr};
+emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;
+addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw
+	nfsroot=${serverip}:${rootpath}
+nfsboot=run initargs; run addnfsargs addipargs;
+	nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} &&
+	nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb &&
+	bootz ${loadaddr} - ${fdt_addr};
diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig
new file mode 100644
index 0000000..709674d
--- /dev/null
+++ b/board/armltd/corstone1000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CORSTONE1000
+
+config SYS_BOARD
+	default "corstone1000"
+
+config SYS_VENDOR
+	default "armltd"
+
+config SYS_CONFIG_NAME
+	default "corstone1000"
+
+endif
diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS
new file mode 100644
index 0000000..8c90568
--- /dev/null
+++ b/board/armltd/corstone1000/MAINTAINERS
@@ -0,0 +1,7 @@
+CORSTONE1000 BOARD
+M:	Rui Miguel Silva <rui.silva@linaro.org>
+M:	Vishnu Banavath <vishnu.banavath@arm.com>
+S:	Maintained
+F:	board/armltd/corstone1000/
+F:	include/configs/corstone1000.h
+F:	configs/corstone1000_defconfig
diff --git a/board/armltd/corstone1000/Makefile b/board/armltd/corstone1000/Makefile
new file mode 100644
index 0000000..77a82c2
--- /dev/null
+++ b/board/armltd/corstone1000/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Arm Limited
+# (C) Copyright 2022 Linaro
+# Rui Miguel Silva <rui.silva@linaro.org>
+
+obj-y	:= corstone1000.o
diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
new file mode 100644
index 0000000..4f4b96a
--- /dev/null
+++ b/board/armltd/corstone1000/corstone1000.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 ARM Limited
+ * (C) Copyright 2022 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <netdev.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+
+static struct mm_region corstone1000_mem_map[] = {
+	{
+		/* CVM */
+		.virt = 0x02000000UL,
+		.phys = 0x02000000UL,
+		.size = 0x02000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	}, {
+		/* QSPI */
+		.virt = 0x08000000UL,
+		.phys = 0x08000000UL,
+		.size = 0x08000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	}, {
+		/* Host Peripherals */
+		.virt = 0x1A000000UL,
+		.phys = 0x1A000000UL,
+		.size = 0x26000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* USB */
+		.virt = 0x40200000UL,
+		.phys = 0x40200000UL,
+		.size = 0x00100000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* ethernet */
+		.virt = 0x40100000UL,
+		.phys = 0x40100000UL,
+		.size = 0x00100000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* OCVM */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = corstone1000_mem_map;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/armltd/corstone1000/corstone1000.env b/board/armltd/corstone1000/corstone1000.env
new file mode 100644
index 0000000..b24ff07
--- /dev/null
+++ b/board/armltd/corstone1000/corstone1000.env
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+usb_pgood_delay=250
+boot_bank_flag=0x08002000
+kernel_addr_bank_0=0x083EE000
+kernel_addr_bank_1=0x0936E000
+retrieve_kernel_load_addr=
+	if itest.l *${boot_bank_flag} == 0; then
+		setenv kernel_addr $kernel_addr_bank_0;
+	else
+		setenv kernel_addr $kernel_addr_bank_1;
+	fi;
+kernel_addr_r=0x88200000
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index ef82f06..50a3830 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -168,7 +168,8 @@ Altera_CYC2_Passive_Serial_fns altera_fns = {
 	altera_post_fn
 };
 
-Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
+#define FPGA_COUNT	1
+Altera_desc altera_fpga[FPGA_COUNT] = {
 	{Altera_CYC2,
 	 passive_serial,
 	 85903,
@@ -182,7 +183,7 @@ int astro5373l_altera_load(void)
 {
 	int i;
 
-	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+	for (i = 0; i < FPGA_COUNT; i++) {
 		/*
 		 * I did not yet manage to get relocation work properly,
 		 * so set stuff here instead of static initialisation:
@@ -372,7 +373,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = {
 	xilinx_fastwr_config_fn
 };
 
-xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc xilinx_fpga[FPGA_COUNT] = {
 	{xilinx_spartan3,
 	 slave_serial,
 	 XILINX_XC3S4000_SIZE,
@@ -388,7 +389,7 @@ int astro5373l_xilinx_load(void)
 
 	fpga_init();
 
-	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+	for (i = 0; i < FPGA_COUNT; i++) {
 		/*
 		 * I did not yet manage to get relocation work properly,
 		 * so set stuff here instead of static initialisation:
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 38f97bc..a9ea9b5 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -74,9 +74,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 0318eea..8a7a960 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -234,9 +234,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 3218e14..c3e1734 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -192,9 +192,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index fcca892..347197a 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -258,9 +258,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index a3fc55b..018fed9 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -176,9 +176,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index f427ee6..af59620 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -169,9 +169,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index e0abe4a..8192824 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -105,9 +105,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
index 00de277..d8f32c9 100644
--- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
+++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
@@ -39,9 +39,6 @@ void board_debug_uart_init(void)
 
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c
index 32e5a2b..7035fab 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -101,9 +101,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
index b69f1c8..65d0a75 100644
--- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
+++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
@@ -65,10 +65,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
-
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
index 67ada27..c38585c 100644
--- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -58,10 +58,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
-
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c
index da697a7..0207770 100644
--- a/board/atmel/sama5d2_icp/sama5d2_icp.c
+++ b/board/atmel/sama5d2_icp/sama5d2_icp.c
@@ -48,9 +48,6 @@ void board_debug_uart_init(void)
 
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 
diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
index cca5bd1..16e9183 100644
--- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
+++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
@@ -108,9 +108,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 4bbb05c..9e0f9c3 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -64,10 +64,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
-
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index c25bf42..a778f26 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -87,9 +87,6 @@ int board_late_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index b6f8dcd..132e7fa 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -140,9 +140,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 2088b48..9fb7e6f 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -102,9 +102,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index 46ec1eb..ba38533 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -100,9 +100,6 @@ void board_debug_uart_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c
index ae18ed0..7d83e76 100644
--- a/board/atmel/sama7g5ek/sama7g5ek.c
+++ b/board/atmel/sama7g5ek/sama7g5ek.c
@@ -48,9 +48,6 @@ void board_debug_uart_init(void)
 
 int board_early_init_f(void)
 {
-#if (IS_ENABLED(CONFIG_DEBUG_UART))
-	debug_uart_init();
-#endif
 	return 0;
 }
 
diff --git a/board/beacon/imx8mm/Kconfig b/board/beacon/imx8mm/Kconfig
index 63f064e..e5d8aa3 100644
--- a/board/beacon/imx8mm/Kconfig
+++ b/board/beacon/imx8mm/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/beacon/imx8mm/imximage-8mm-lpddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index 12266b2..a93cc93 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -59,31 +59,6 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-	return 0;
-}
-
 static int power_init_board(void)
 {
 	struct udevice *dev;
@@ -124,12 +99,8 @@ void board_init_f(ulong dummy)
 
 	init_uart_clk(1);
 
-	board_early_init_f();
-
 	timer_init();
 
-	preloader_console_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -139,6 +110,8 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	preloader_console_init();
+
 	ret = uclass_get_device_by_name(UCLASS_CLK,
 					"clock-controller@30380000",
 					&dev);
diff --git a/board/beacon/imx8mn/Kconfig b/board/beacon/imx8mn/Kconfig
index fb30139..e11286c 100644
--- a/board/beacon/imx8mn/Kconfig
+++ b/board/beacon/imx8mn/Kconfig
@@ -18,6 +18,4 @@ config IMX8MN_BEACON_2GB_LPDDR
 config IMX_CONFIG
 	default "board/beacon/imx8mn/imximage-8mn-lpddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index bb51be0..029f71b 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -68,34 +68,17 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
 
 static iomux_v3_cfg_t const pwm_pads[] = {
 	IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
 int board_early_init_f(void)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
 	/* Claiming pwm pins prevents LCD flicker during startup*/
 	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
 
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 	init_uart_clk(1);
 
 	return 0;
@@ -114,14 +97,14 @@ void board_init_f(ulong dummy)
 
 	timer_init();
 
-	preloader_console_init();
-
 	ret = spl_init();
 	if (ret) {
 		debug("spl_init() failed: %d\n", ret);
 		hang();
 	}
 
+	preloader_console_init();
+
 	enable_tzc380();
 
 	/* DDR initialization */
diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig
new file mode 100644
index 0000000..63d4252
--- /dev/null
+++ b/board/broadcom/bcmbca/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+config SYS_BOARD
+	default "bcmbca"
+
+config SYS_VENDOR
+	default "broadcom"
+
+if TARGET_BCM947622
+
+config SYS_CONFIG_NAME
+	default "bcm947622"
+
+endif
diff --git a/board/broadcom/bcmbca/Makefile b/board/broadcom/bcmbca/Makefile
new file mode 100644
index 0000000..8f06c31
--- /dev/null
+++ b/board/broadcom/bcmbca/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+
+obj-y	+= board.o
diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c
new file mode 100644
index 0000000..4aa1d65
--- /dev/null
+++ b/board/broadcom/bcmbca/board.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		puts("fdtdec_setup_mem_size_base() has failed\n");
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/bsh/imx8mn_smm_s2/Kconfig b/board/bsh/imx8mn_smm_s2/Kconfig
index f43d058..041a9c7 100644
--- a/board/bsh/imx8mn_smm_s2/Kconfig
+++ b/board/bsh/imx8mn_smm_s2/Kconfig
@@ -22,8 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select BSH_SMM_S2_DDR3L_256
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_IMX8MN_BSH_SMM_S2PRO
@@ -44,6 +42,4 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select BSH_SMM_S2_DDR3L_512
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
index b00e466..4993880 100644
--- a/board/compulab/cm_t335/u-boot.lds
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -36,8 +36,8 @@ SECTIONS
 	. = .;
 
 	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
 	}
 
 	. = ALIGN(4);
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c
index 2dc62d6..d2d2026 100644
--- a/board/compulab/imx8mm-cl-iot-gate/spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -83,31 +83,6 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-	return 0;
-}
-
 static int power_init_board(void)
 {
 	struct udevice *dev;
@@ -149,14 +124,10 @@ void board_init_f(ulong dummy)
 
 	arch_cpu_init();
 
-	board_early_init_f();
-
 	init_uart_clk(2);
 
 	timer_init();
 
-	preloader_console_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -166,6 +137,8 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	preloader_console_init();
+
 	ret = uclass_get_device_by_name(UCLASS_CLK,
 					"clock-controller@30380000",
 					&dev);
diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig
index d4a238d..a1f2139 100644
--- a/board/congatec/common/Kconfig
+++ b/board/congatec/common/Kconfig
@@ -1,44 +1,3 @@
-if !ARCH_IMX8M && !ARCH_IMX8
-
-config CHAIN_OF_TRUST
-	depends on !FIT_SIGNATURE && SECURE_BOOT
-	imply CMD_BLOB
-	imply CMD_HASH if ARM
-	select FSL_CAAM
-	select SPL_BOARD_INIT if (ARM && SPL)
-	select SHA_HW_ACCEL
-	select SHA_PROG_HW_ACCEL
-	select ENV_IS_NOWHERE
-	select CMD_EXT4 if ARM
-	select CMD_EXT4_WRITE if ARM
-	bool
-	default y
-
-config CMD_ESBC_VALIDATE
-	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
-	default y if CHAIN_OF_TRUST
-	help
-	  This option enables two commands used for secure booting:
-
-	    esbc_validate - validate signature using RSA verification
-	    esbc_halt - put the core in spin loop (Secure Boot Only)
-
-endif
-
-config VOL_MONITOR_LTC3882_READ
-	depends on VID
-	bool "Enable the LTC3882 voltage monitor read"
-	help
-	 This option enables LTC3882 voltage monitor read
-	 functionality. It is used by common VID driver.
-
-config VOL_MONITOR_LTC3882_SET
-	depends on VID
-	bool "Enable the LTC3882 voltage monitor set"
-	help
-	 This option enables LTC3882 voltage monitor set
-	 functionality. It is used by common VID driver.
-
 config USB_TCPC
 	bool "USB Typec port controller simple driver"
 	help
diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile
index d4ddfbf..2db0fc1 100644
--- a/board/congatec/common/Makefile
+++ b/board/congatec/common/Makefile
@@ -8,10 +8,12 @@
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_INIT_MINIMAL
 MINIMAL=y
 endif
 endif
+endif
 
 ifdef MINIMAL
 # necessary to create built-in.o
diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/MCR3000/u-boot.lds
index 70aef32..24b535e 100644
--- a/board/cssi/MCR3000/u-boot.lds
+++ b/board/cssi/MCR3000/u-boot.lds
@@ -59,8 +59,8 @@ SECTIONS
 	. = .;
 
 	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
 	}
 
 	. = .;
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index 8f04911..7e0f09f 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -11,7 +11,7 @@ MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
 		LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
 
 MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
-                LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+                LENGTH = 0x1080000 }
 
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
@@ -36,7 +36,7 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
-	.u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
+	__u_boot_list : { KEEP(*(SORT(__u_boot_list*))); } >.sram
 
 	. = ALIGN(4);
 	.rel.dyn : {
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index d407f0b..7a4c08c 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -9,7 +9,6 @@
 #include <net.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <bootm.h>
@@ -78,11 +77,6 @@
 #define SYSCFG_PMCSETR_ETH_SEL_RGMII	BIT(21)
 #define SYSCFG_PMCSETR_ETH_SEL_RMII	BIT(23)
 
-/*
- * Get a global data pointer
- */
-DECLARE_GLOBAL_DATA_PTR;
-
 #define KS_CCR		0x08
 #define KS_CCR_EEPROM	BIT(9)
 #define KS_BE0		BIT(12)
@@ -96,14 +90,15 @@ int setup_mac_address(void)
 	bool skip_eth0 = false;
 	bool skip_eth1 = false;
 	struct udevice *dev;
-	int off, ret;
+	int ret;
+	ofnode node;
 
 	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
 	if (ret)	/* ethaddr is already set */
 		skip_eth0 = true;
 
-	off = fdt_path_offset(gd->fdt_blob, "ethernet1");
-	if (off < 0) {
+	node = ofnode_path("ethernet1");
+	if (!ofnode_valid(node)) {
 		/* ethernet1 is not present in the system */
 		skip_eth1 = true;
 		goto out_set_ethaddr;
@@ -116,7 +111,7 @@ int setup_mac_address(void)
 		goto out_set_ethaddr;
 	}
 
-	ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
+	ret = ofnode_device_is_compatible(node, "micrel,ks8851-mll");
 	if (ret)
 		goto out_set_ethaddr;
 
@@ -127,7 +122,7 @@ int setup_mac_address(void)
 	 * MAC address.
 	 */
 	u32 reg, cider, ccr;
-	reg = fdt_get_base_address(gd->fdt_blob, off);
+	reg = ofnode_get_addr(node);
 	if (!reg)
 		goto out_set_ethaddr;
 
@@ -149,13 +144,13 @@ out_set_ethaddr:
 	if (skip_eth0 && skip_eth1)
 		return 0;
 
-	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
-	if (off < 0) {
+	node = ofnode_path("eeprom0");
+	if (!ofnode_valid(node)) {
 		printf("%s: No eeprom0 path offset\n", __func__);
-		return off;
+		return -ENOENT;
 	}
 
-	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
 	if (ret) {
 		printf("Cannot find EEPROM!\n");
 		return ret;
@@ -191,8 +186,8 @@ int checkboard(void)
 		mode = "basic";
 
 	printf("Board: stm32mp1 in %s mode", mode);
-	fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
-				 &fdt_compat_len);
+	fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+					 &fdt_compat_len);
 	if (fdt_compat && fdt_compat_len)
 		printf(" (%s)", fdt_compat);
 	puts("\n");
@@ -289,7 +284,7 @@ int board_fit_config_name_match(const char *name)
 	const char *compat;
 	char test[128];
 
-	compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
+	compat = ofnode_get_property(ofnode_root(), "compatible", NULL);
 
 	snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
 		compat, somcode, brdcode);
@@ -604,14 +599,13 @@ static void board_init_fmc2(void)
 #define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(n)	((((n) - 1) & 3) * 2)
 static int board_get_regulator_buck3_nvm_uv_av96(int *uv)
 {
-	const void *fdt = gd->fdt_blob;
 	struct udevice *dev;
 	u8 bucks_vout = 0;
 	const char *prop;
 	int len, ret;
 
 	/* Check whether this is Avenger96 board. */
-	prop = fdt_getprop(fdt, 0, "compatible", &len);
+	prop = ofnode_get_property(ofnode_root(), "compatible", &len);
 	if (!prop || !len)
 		return -ENODEV;
 
@@ -701,8 +695,8 @@ int board_late_init(void)
 	const void *fdt_compat;
 	int fdt_compat_len;
 
-	fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
-				 &fdt_compat_len);
+	fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+					 &fdt_compat_len);
 	if (fdt_compat && fdt_compat_len) {
 		if (strncmp(fdt_compat, "st,", 3) != 0)
 			env_set("board_name", fdt_compat);
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index 2b483da..1054837 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -273,7 +273,7 @@ void board_debug_uart_init(void)
 	setup_early_clocks();
 
 	/* done by pin controller driver if not debugging */
-	enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
+	enable_uart_pin_mux(CONFIG_VAL(DEBUG_UART_BASE));
 }
 #endif
 
diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c
index 348fcf3..99edaa3 100644
--- a/board/emulation/qemu-ppce500/qemu-ppce500.c
+++ b/board/emulation/qemu-ppce500/qemu-ppce500.c
@@ -32,6 +32,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Virtual address range for PCI region maps */
+#define SYS_PCI_MAP_START	0x80000000
+#define SYS_PCI_MAP_END		0xe0000000
+
 static void *get_fdt_virt(void)
 {
 	if (gd->flags & GD_FLG_RELOC)
@@ -101,7 +105,7 @@ static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr)
 	map_addr += size - 1;
 	map_addr &= ~(size - 1);
 
-	if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
+	if (map_addr + size >= SYS_PCI_MAP_END)
 		return -1;
 
 	/* Map virtual memory for range */
@@ -137,7 +141,7 @@ int misc_init_r(void)
 	pci_get_regions(dev, &io, &mem, &pre);
 
 	/* Start MMIO and PIO range maps above RAM */
-	map_addr = CONFIG_SYS_PCI_MAP_START;
+	map_addr = SYS_PCI_MAP_START;
 
 	/* Map MMIO range */
 	ret = pci_map_region(mem->phys_start, mem->size, &map_addr);
diff --git a/board/engicam/imx8mm/Kconfig b/board/engicam/imx8mm/Kconfig
index 5495b3b..3b3b93b 100644
--- a/board/engicam/imx8mm/Kconfig
+++ b/board/engicam/imx8mm/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
index f9be769..1846134 100644
--- a/board/engicam/imx8mm/spl.c
+++ b/board/engicam/imx8mm/spl.c
@@ -54,19 +54,9 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 int board_early_init_f(void)
 {
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-	return 0;
+       return 0;
 }
 
 void board_init_f(ulong dummy)
@@ -81,8 +71,6 @@ void board_init_f(ulong dummy)
 
 	timer_init();
 
-	preloader_console_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -92,6 +80,8 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	preloader_console_init();
+
 	enable_tzc380();
 
 	/* DDR initialization */
diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c
index 20d8603..0a3e580 100644
--- a/board/engicam/stm32mp1/stm32mp1.c
+++ b/board/engicam/stm32mp1/stm32mp1.c
@@ -14,8 +14,6 @@
 #include <asm/arch/sys_proto.h>
 #include <power/regulator.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	char *mode;
@@ -28,8 +26,8 @@ int checkboard(void)
 		mode = "basic";
 
 	printf("Board: stm32mp1 in %s mode", mode);
-	fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
-				 &fdt_compat_len);
+	fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+					 &fdt_compat_len);
 	if (fdt_compat && fdt_compat_len)
 		printf(" (%s)", fdt_compat);
 	puts("\n");
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
deleted file mode 100644
index b0e6e43..0000000
--- a/board/freescale/common/Kconfig
+++ /dev/null
@@ -1,110 +0,0 @@
-config CHAIN_OF_TRUST
-	depends on !FIT_SIGNATURE && NXP_ESBC
-	imply CMD_BLOB
-	imply CMD_HASH if ARM
-	select FSL_CAAM
-	select ARCH_MISC_INIT
-	select SPL_BOARD_INIT if (ARM && SPL)
-	select SPL_HASH if (ARM && SPL)
-	select SHA_HW_ACCEL
-	select SHA_PROG_HW_ACCEL
-	select ENV_IS_NOWHERE
-	select CMD_EXT4 if ARM
-	select CMD_EXT4_WRITE if ARM
-	bool
-	default y
-
-config CMD_ESBC_VALIDATE
-	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
-	default y if CHAIN_OF_TRUST
-	help
-	  This option enables two commands used for secure booting:
-
-	    esbc_validate - validate signature using RSA verification
-	    esbc_halt - put the core in spin loop (Secure Boot Only)
-
-config DEEP_SLEEP
-	bool "Enable SoC deep sleep feature"
-	default y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
-	help
-	  Indicates this SoC supports deep sleep feature. If deep sleep is
-	  supported, core will start to execute uboot when wakes up.
-
-config FSL_USE_PCA9547_MUX
-	bool "Enable PCA9547 I2C Mux on Freescale boards"
-	help
-	 This option enables the PCA9547 I2C mux on Freescale boards.
-
-config VID
-	bool "Enable Freescale VID"
-	depends on I2C || DM_I2C
-	help
-	 This option enables setting core voltage based on individual
-	 values saved in SoC fuses.
-
-config SPL_VID
-	bool "Enable Freescale VID in SPL"
-	depends on I2C || DM_I2C
-	help
-	 This option enables setting core voltage based on individual
-	 values saved in SoC fuses, in SPL.
-
-if VID || SPL_VID
-
-config VID_FLS_ENV
-	string "Environment variable for overriding VDD"
-	help
-	  This option allows for specifying the environment variable
-	  to check to override VDD information.
-
-config VOL_MONITOR_INA220
-	bool "Enable the INA220 voltage monitor read"
-	help
-	  This option enables INA220 voltage monitor read
-	  functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_IR36021_READ
-	bool "Enable the IR36021 voltage monitor read"
-	help
-	 This option enables IR36021 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_IR36021_SET
-	bool "Enable the IR36021 voltage monitor set"
-	help
-	 This option enables IR36021 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_LTC3882_READ
-	bool "Enable the LTC3882 voltage monitor read"
-	help
-	 This option enables LTC3882 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_LTC3882_SET
-	bool "Enable the LTC3882 voltage monitor set"
-	help
-	 This option enables LTC3882 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_ISL68233_READ
-	bool "Enable the ISL68233 voltage monitor read"
-	help
-	 This option enables ISL68233 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_ISL68233_SET
-	bool "Enable the ISL68233 voltage monitor set"
-	help
-	 This option enables ISL68233 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-endif
-
-config FSL_QIXIS
-	bool "Enable QIXIS support"
-
-config QIXIS_I2C_ACCESS
-	bool "Access to QIXIS is over i2c"
-	depends on FSL_QIXIS
-	default y
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 4df4849..4214c6e 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -6,10 +6,12 @@
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_INIT_MINIMAL
 MINIMAL=y
 endif
 endif
+endif
 
 ifdef MINIMAL
 # necessary to create built-in.o
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index 7ffb315..d31fb82 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -12,6 +12,7 @@
 #include <fsl_sfp.h>
 #include <log.h>
 #include <dm/root.h>
+#include <asm/fsl_secure_boot.h>
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
 #include <spl.h>
@@ -76,14 +77,14 @@ int fsl_setenv_chain_of_trust(void)
 
 	/* If Boot mode is Secure, set the environment variables
 	 * bootdelay = 0 (To disable Boot Prompt)
-	 * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+	 * bootcmd = CHAIN_BOOT_CMD (Validate and execute Boot script)
 	 */
 	env_set("bootdelay", "-2");
 
 #ifdef CONFIG_ARM
 	env_set("secureboot", "y");
 #else
-	env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+	env_set("bootcmd", CHAIN_BOOT_CMD);
 #endif
 
 	return 0;
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 34875d0..f1a0b0c 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -871,7 +871,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
 	int ret, i, hash_cmd = 0;
 	u32 srk_hash[8];
 
-	if (arg_hash_str != NULL) {
+	if (strlen(arg_hash_str) != 0) {
 		const char *cp = arg_hash_str;
 		int i = 0;
 
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 0860bd2..af76327 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -166,4 +166,25 @@ defined(CONFIG_TARGET_LX2160ARDB)
 #define QIXIS_ESDHC_NO_ADAPTER		0x7
 #endif
 
+/*
+ * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
+ */
+static inline u8 qixis_esdhc_detect_quirk(void)
+{
+	/*
+	 * SDHC1 Card ID:
+	 * Specifies the type of card installed in the SDHC1 adapter slot.
+	 * 000= (reserved)
+	 * 001= eMMC V4.5 adapter is installed.
+	 * 010= SD/MMC 3.3V adapter is installed.
+	 * 011= eMMC V4.4 adapter is installed.
+	 * 100= eMMC V5.0 adapter is installed.
+	 * 101= MMC card/Legacy (3.3V) adapter is installed.
+	 * 110= SDCard V2/V3 adapter installed.
+	 * 111= no adapter is installed.
+	 */
+	return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
+		 QIXIS_ESDHC_NO_ADAPTER);
+}
+
 #endif
diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
index e92b0d0..dbcd1af 100644
--- a/board/freescale/corenet_ds/Kconfig
+++ b/board/freescale/corenet_ds/Kconfig
@@ -9,8 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P3041DS"
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_P4080DS
@@ -24,8 +22,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P4080DS"
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_P5040DS
@@ -39,6 +35,4 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P5040DS"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
index 3469064..9839eac 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -62,7 +62,6 @@
 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
 #define CONFIG_SYS_DDR_TIMING_4		0x00000001
 #define CONFIG_SYS_DDR_TIMING_5		0x02401400
 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig
index 0adf87b..a148a9b 100644
--- a/board/freescale/imx8mn_evk/Kconfig
+++ b/board/freescale/imx8mn_evk/Kconfig
@@ -15,6 +15,4 @@ config IMX8MN_LOW_DRIVE_MODE
 config IMX_CONFIG
 	default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8mp_evk/Kconfig b/board/freescale/imx8mp_evk/Kconfig
index 42625fd..cafa632 100644
--- a/board/freescale/imx8mp_evk/Kconfig
+++ b/board/freescale/imx8mp_evk/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig
index aed6ab2..5f2413f 100644
--- a/board/freescale/imx8qm_mek/Kconfig
+++ b/board/freescale/imx8qm_mek/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/imx8qm_mek/imximage.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig
index b9aab37..6533b4d 100644
--- a/board/freescale/imx8qxp_mek/Kconfig
+++ b/board/freescale/imx8qxp_mek/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/imx8qxp_mek/imximage.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig
index 1e461ee..4637b96 100644
--- a/board/freescale/imx8ulp_evk/Kconfig
+++ b/board/freescale/imx8ulp_evk/Kconfig
@@ -9,6 +9,4 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "imx8ulp_evk"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index 4ac69d7..75de782af 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -89,7 +89,3 @@ config SYS_LS_PFE_ESBC_LENGTH
 	hex "length of PFE Firmware HDR"
 	default 0xc00
 endif
-
-if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
-source "board/freescale/common/Kconfig"
-endif
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index 59b1a87..991ba60 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -77,7 +77,4 @@ config PFE_SGMII_2500_PHY2_ADDR
 
 endif
 
-
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index c4acea3..aa15f5a 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -63,8 +63,6 @@ config PFE_EMAC2_PHY_ADDR
 
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_LS1012A2G5RDB
@@ -119,6 +117,4 @@ config PFE_EMAC2_PHY_ADDR
 
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig
index c6b1606..4a12c16 100644
--- a/board/freescale/ls1021aiot/Kconfig
+++ b/board/freescale/ls1021aiot/Kconfig
@@ -12,6 +12,4 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1021aiot"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig
index 60b8472..119b955 100644
--- a/board/freescale/ls1021aqds/Kconfig
+++ b/board/freescale/ls1021aqds/Kconfig
@@ -12,6 +12,4 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1021aqds"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1021atsn/Kconfig b/board/freescale/ls1021atsn/Kconfig
index d999fa4..aa42a06 100644
--- a/board/freescale/ls1021atsn/Kconfig
+++ b/board/freescale/ls1021atsn/Kconfig
@@ -13,6 +13,4 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1021atsn"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig
index a4641cb..bc50b8d 100644
--- a/board/freescale/ls1021atwr/Kconfig
+++ b/board/freescale/ls1021atwr/Kconfig
@@ -12,6 +12,4 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1021atwr"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
index 4093981..5c27f0f 100644
--- a/board/freescale/ls1028a/Kconfig
+++ b/board/freescale/ls1028a/Kconfig
@@ -32,8 +32,6 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_LS1028ARDB
@@ -58,6 +56,4 @@ config SYS_TEXT_BASE
 	default 0x82000000 if TFABOOT
 	default 0x20100000
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 71a086e..1a7806f 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019, 2021 NXP
+ * Copyright 2019-2022 NXP
  */
 
 #include <common.h>
@@ -328,3 +328,8 @@ int checkboard(void)
 	return 0;
 }
 #endif
+
+void *video_hw_init(void)
+{
+	return NULL;
+}
diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig
index 182900e..4be445e 100644
--- a/board/freescale/ls1043aqds/Kconfig
+++ b/board/freescale/ls1043aqds/Kconfig
@@ -28,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
index d66c780..56502f9 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -27,6 +27,4 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig
index 6a4c3e9..68329d7 100644
--- a/board/freescale/ls1046afrwy/Kconfig
+++ b/board/freescale/ls1046afrwy/Kconfig
@@ -13,5 +13,4 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1046afrwy"
 
-source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig
index 1616dcc..adf325f 100644
--- a/board/freescale/ls1046aqds/Kconfig
+++ b/board/freescale/ls1046aqds/Kconfig
@@ -28,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig
index 4c31e0e..1fb391c 100644
--- a/board/freescale/ls1046ardb/Kconfig
+++ b/board/freescale/ls1046ardb/Kconfig
@@ -27,5 +27,4 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig
index 8bb828e..f1a4523 100644
--- a/board/freescale/ls1088a/Kconfig
+++ b/board/freescale/ls1088a/Kconfig
@@ -26,7 +26,6 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
 endif
 
 if TARGET_LS1088ARDB
@@ -57,5 +56,4 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig
index 6b2b645..1036f33 100644
--- a/board/freescale/ls2080aqds/Kconfig
+++ b/board/freescale/ls2080aqds/Kconfig
@@ -29,6 +29,4 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index 678d582..c8b0b94 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -12,8 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls2080ardb"
 
-source "board/freescale/common/Kconfig"
-
 if FSL_LS_PPA
 config SYS_LS_PPA_FW_ADDR
 	hex "PPA Firmware Addr"
@@ -30,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig
index 7556f7d..0e4b415 100644
--- a/board/freescale/lx2160a/Kconfig
+++ b/board/freescale/lx2160a/Kconfig
@@ -12,7 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "lx2160ardb"
 
-source "board/freescale/common/Kconfig"
 endif
 
 if TARGET_LX2160AQDS
@@ -29,7 +28,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "lx2160aqds"
 
-source "board/freescale/common/Kconfig"
 endif
 
 if TARGET_LX2162AQDS
@@ -46,5 +44,4 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "lx2162aqds"
 
-source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 49d96d3..a078643 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -356,27 +356,6 @@ int checkboard(void)
 }
 
 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
-/*
- * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
- */
-u8 qixis_esdhc_detect_quirk(void)
-{
-	/*
-	 * SDHC1 Card ID:
-	 * Specifies the type of card installed in the SDHC1 adapter slot.
-	 * 000= (reserved)
-	 * 001= eMMC V4.5 adapter is installed.
-	 * 010= SD/MMC 3.3V adapter is installed.
-	 * 011= eMMC V4.4 adapter is installed.
-	 * 100= eMMC V5.0 adapter is installed.
-	 * 101= MMC card/Legacy (3.3V) adapter is installed.
-	 * 110= SDCard V2/V3 adapter installed.
-	 * 111= no adapter is installed.
-	 */
-	return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
-		 QIXIS_ESDHC_NO_ADAPTER);
-}
-
 static void esdhc_adapter_card_ident(void)
 {
 	u8 card_id, val;
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 2a47035..85f5f0c 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -93,11 +93,6 @@ int testdram(void)
 
 #ifdef CONFIG_IDE
 #include <ata.h>
-int ide_preinit(void)
-{
-	return (0);
-}
-
 void ide_set_reset(int idereset)
 {
 	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig
index 87f3374..bd9153b 100644
--- a/board/freescale/mpc8548cds/Kconfig
+++ b/board/freescale/mpc8548cds/Kconfig
@@ -1,5 +1,8 @@
 if TARGET_MPC8548CDS
 
+config PCI1
+	def_bool y
+
 config SYS_BOARD
 	default "mpc8548cds"
 
diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig
index 3adac4a..159bcc4 100644
--- a/board/freescale/p1010rdb/Kconfig
+++ b/board/freescale/p1010rdb/Kconfig
@@ -9,6 +9,4 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P1010RDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index 36b34c7..a00806e 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -5,10 +5,12 @@
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_INIT_MINIMAL
 MINIMAL=y
 endif
 endif
+endif
 
 ifdef MINIMAL
 obj-y	+= spl_minimal.o
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 7eaa204..8869500 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -57,24 +57,24 @@ void board_init_f(ulong bootflag)
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
 	*/
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+	relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE);
 }
 
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
 	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	gd = (gd_t *)CONFIG_VAL(GD_ADDR);
 	struct bd_info *bd;
 
 	memset(gd, 0, sizeof(gd_t));
-	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
 
 	arch_cpu_init();
 	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR),
+			CONFIG_VAL(RELOC_MALLOC_SIZE));
 	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifndef CONFIG_SPL_NAND_BOOT
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 04faefe..7992666 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -72,8 +72,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) || \
-	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index a7736d8..cbdb250 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -5,10 +5,12 @@
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_INIT_MINIMAL
 MINIMAL=y
 endif
 endif
+endif
 
 ifdef MINIMAL
 obj-y	+= spl_minimal.o
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index be803dd..038e673 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -227,7 +227,7 @@ phys_size_t fixed_sdram(void)
 		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
 		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
-		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+		.ddr_data_init = 0xdeadbeef, /* Poison value */
 		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
 		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 5f4d713..6bdfb35 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -9,7 +9,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_VSC7385_ENET
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 6665aa4..56bc355 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -83,6 +83,12 @@ struct cpld_data {
 #define CPLD_FXS_LED	0x0F
 #define CPLD_SYS_RST	0x00
 
+void board_reset(void)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	out_8(&cpld_data->system_rst, 1);
+}
+
 void board_cpld_init(void)
 {
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@@ -154,7 +160,9 @@ int board_early_init_f(void)
 	clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
 
 	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
+#endif
 
 	board_gpio_init();
 	board_cpld_init();
@@ -178,7 +186,11 @@ int checkboard(void)
 	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
 
 	/* FIXME: This should just use the model from the device tree or similar */
-	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", BOARD_NAME,
+#ifdef BOARD_NAME
+	printf("Board: %s ", BOARD_NAME);
+#endif
+
+	printf("CPLD: V%d.%d PCBA: V%d.0\n",
 		in_8(&cpld_data->cpld_rev_major) & 0x0F,
 		in_8(&cpld_data->cpld_rev_minor) & 0x0F,
 		in_8(&cpld_data->pcba_rev) & 0x0F);
@@ -216,8 +228,11 @@ int checkboard(void)
 	val = (in & io_config) | (out & (~io_config));
 
 	puts("rom_loc: ");
-	if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
+	if (0) {
+#ifdef __SW_BOOT_SD
+	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
 		puts("sd");
+#endif
 #ifdef __SW_BOOT_SD2
 	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) {
 		puts("sd");
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 22156f2..b60027e 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -63,24 +63,24 @@ void board_init_f(ulong bootflag)
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
 	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+	relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE);
 }
 
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
 	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	gd = (gd_t *)CONFIG_VAL(GD_ADDR);
 	struct bd_info *bd;
 
 	memset(gd, 0, sizeof(gd_t));
-	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
 
 	arch_cpu_init();
 	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR),
+			CONFIG_VAL(RELOC_MALLOC_SIZE));
 	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_ENV_SUPPORT
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 5931ec6..38843a9 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -65,9 +65,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 10, BOOKE_PAGESZ_64K, 1),
 #endif /* not SPL */
 
 #ifdef CONFIG_SYS_NAND_BASE
@@ -77,8 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT) || \
-	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
 	/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig
index 7e187dd..78e1121 100644
--- a/board/freescale/p2041rdb/Kconfig
+++ b/board/freescale/p2041rdb/Kconfig
@@ -9,6 +9,4 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P2041RDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 5bd2b99..2a84e9b 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -229,7 +229,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#if defined(CONFIG_HAS_FSL_DR_USB)
 	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig
index 6deeb24..d538386 100644
--- a/board/freescale/t102xrdb/Kconfig
+++ b/board/freescale/t102xrdb/Kconfig
@@ -9,6 +9,4 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T102xRDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig
index e6e46fa..e33d317 100644
--- a/board/freescale/t104xrdb/Kconfig
+++ b/board/freescale/t104xrdb/Kconfig
@@ -11,6 +11,4 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T104xRDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig
index 58a31b6..c419a59 100644
--- a/board/freescale/t208xqds/Kconfig
+++ b/board/freescale/t208xqds/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config SRIO_PCIE_BOOT_SLAVE
 	bool "Boot as a SRIO PCIe slave device"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig
index d4c061a..35d884e 100644
--- a/board/freescale/t208xrdb/Kconfig
+++ b/board/freescale/t208xrdb/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config T2080RDB_REV_D
 	bool "Support for T2080RDB revisions D and up"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
index 542e574..d93e453 100644
--- a/board/freescale/t4rdb/Kconfig
+++ b/board/freescale/t4rdb/Kconfig
@@ -9,6 +9,4 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T4240RDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/friendlyarm/Kconfig b/board/friendlyarm/Kconfig
index f8f9cfd..fa04727 100644
--- a/board/friendlyarm/Kconfig
+++ b/board/friendlyarm/Kconfig
@@ -11,6 +11,7 @@ config S5P4418_ONEWIRE
 
 config PWM_NX
 	bool "PWM"
+	select PWM_S5P
 	help
 	  This enables LCD-Backlight control via PWM.
 endchoice
diff --git a/board/gateworks/gw_ventana/gw_ventana.env b/board/gateworks/gw_ventana/gw_ventana.env
new file mode 100644
index 0000000..9a316c7
--- /dev/null
+++ b/board/gateworks/gw_ventana/gw_ventana.env
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ */
+
+splashpos=m,m
+splashimage=CONFIG_SYS_LOAD_ADDR
+usb_pgood_delay=2000
+console=ttymxc1
+bootdevs=usb mmc sata flash
+hwconfig=_UNKNOWN_
+
+disk=0
+part=1
+
+fdt_high=0xffffffff
+fdt_addr=0x18000000
+initrd_high=0xffffffff
+fixfdt=fdt addr ${fdt_addr}
+bootdir=boot
+loadfdt=
+	if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then
+		echo Loaded DTB from ${bootdir}/${fdt_file};
+		run fixfdt;
+	elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then
+		echo Loaded DTB from ${bootdir}/${fdt_file1};
+		run fixfdt;
+	elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then
+		echo Loaded DTB from ${bootdir}/${fdt_file2};
+		run fixfdt;
+	fi
+
+fs=ext4
+script=6x_bootscript-ventana
+loadscript=
+	if ${fsload} ${loadaddr} ${bootdir}/${script}; then
+		source ${loadaddr};
+	fi
+
+uimage=uImage
+mmc_root=mmcblk0p1
+mmc_boot=
+	setenv fsload "${fs}load mmc ${disk}:${part}";
+	mmc dev ${disk} && mmc rescan &&
+	setenv dtype mmc; run loadscript;
+	if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then
+		setenv bootargs console=${console},${baudrate}
+			root=/dev/${mmc_root} rootfstype=${fs}
+			rootwait rw ${video} ${extra};
+		if run loadfdt; then
+			bootm ${loadaddr} - ${fdt_addr};
+		else
+			bootm;
+		fi;
+	fi
+
+sata_boot=
+	setenv fsload "${fs}load sata ${disk}:${part}";
+	sata init &&
+	setenv dtype sata; run loadscript;
+	if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then
+		setenv bootargs console=${console},${baudrate}
+			root=/dev/sda1 rootfstype=${fs}
+			rootwait rw ${video} ${extra};
+		if run loadfdt; then
+			bootm ${loadaddr} - ${fdt_addr};
+		else
+			bootm;
+		fi;
+	fi
+
+usb_boot=
+	setenv fsload "${fs}load usb ${disk}:${part}";
+	usb start && usb dev ${disk} &&
+	setenv dtype usb; run loadscript;
+	if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then
+		setenv bootargs console=${console},${baudrate}
+			root=/dev/sda1 rootfstype=${fs}
+			rootwait rw ${video} ${extra};
+		if run loadfdt; then
+			bootm ${loadaddr} - ${fdt_addr};
+		else
+			bootm;
+		fi;
+	fi
+
+#ifdef CONFIG_SPI_FLASH
+image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin
+image_uboot=ventana/u-boot_spi.imx
+
+spi_koffset=0x90000
+spi_klen=0x200000
+
+spi_updateuboot=echo Updating uboot from
+	${serverip}:${image_uboot}...;
+	tftpboot ${loadaddr} ${image_uboot} &&
+	sf probe && sf erase 0 80000 &&
+		sf write ${loadaddr} 400 ${filesize}
+spi_update=echo Updating OS from ${serverip}:${image_os}
+	to ${spi_koffset} ...;
+	tftp ${loadaddr} ${image_os} &&
+	sf probe &&
+	sf update ${loadaddr} ${spi_koffset} ${filesize}
+
+flash_boot=
+	if sf probe &&
+	sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then
+		setenv bootargs console=${console},${baudrate}
+			root=/dev/mtdblock3
+			rootfstype=squashfs,jffs2
+			${video} ${extra};
+		bootm;
+	fi
+#else
+image_rootfs=openwrt-imx6-ventana-rootfs.ubi
+nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...;
+	tftp ${loadaddr} ${image_rootfs} &&
+	nand erase.part rootfs &&
+	nand write ${loadaddr} rootfs ${filesize}
+
+flash_boot=
+	setenv fsload 'ubifsload';
+	ubi part rootfs;
+	if ubi check boot; then
+		ubifsmount ubi0:boot;
+		setenv root ubi0:rootfs ubi.mtd=2
+			rootfstype=squashfs,ubifs;
+		setenv bootdir;
+	elif ubi check rootfs; then
+		ubifsmount ubi0:rootfs;
+		setenv root ubi0:rootfs ubi.mtd=2
+			rootfstype=ubifs;
+	fi;
+	setenv dtype nand; run loadscript;
+	if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then
+		setenv bootargs console=${console},${baudrate}
+			root=${root} ${video} ${extra};
+		if run loadfdt; then
+			ubifsumount;
+			bootm ${loadaddr} - ${fdt_addr};
+		else
+			ubifsumount; bootm;
+		fi;
+	fi
+#endif
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 6e6ce01..4c0feb4 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -87,33 +87,6 @@ static void spl_dram_init(int size)
 	ddr_init(dram_timing);
 }
 
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-#ifdef CONFIG_IMX8MM
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#elif CONFIG_IMX8MN
-static const iomux_v3_cfg_t wdog_pads[] = {
-	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#elif CONFIG_IMX8MP
-static const iomux_v3_cfg_t wdog_pads[] = {
-	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#endif
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	return 0;
-}
-
 /*
  * Model specific PMIC adjustments necessary prior to DRAM init
  *
@@ -253,8 +226,6 @@ void board_init_f(ulong dummy)
 
 	init_uart_clk(1);
 
-	board_early_init_f();
-
 	timer_init();
 
 	/* Clear the BSS. */
diff --git a/board/hpe/gxp/Kconfig b/board/hpe/gxp/Kconfig
new file mode 100644
index 0000000..5b154a3
--- /dev/null
+++ b/board/hpe/gxp/Kconfig
@@ -0,0 +1,46 @@
+choice
+	prompt "SoC select"
+
+config TARGET_GXP
+	bool "GXP"
+	select DM
+	select SOC_GXP
+	imply CMD_DM
+
+config TARGET_GXP2
+	bool "GXP2"
+	select DM
+	select SOC_GXP
+	select GXP_ECC
+	imply CMD_DM
+
+endchoice
+
+choice
+	prompt "GXP VROM size"
+	default GXP_VROM_64MB
+	optional
+
+config GXP_VROM_64MB
+	bool "64MB"
+
+config GXP_VROM_32MB
+	bool "32MB"
+endchoice
+
+config GXP_ECC
+	bool "Enable memory ECC protected"
+	help
+	  Use half of memory to enable ECC protected
+
+config SYS_BOARD
+	default "gxp"
+
+config SYS_VENDOR
+	default "hpe"
+
+config SYS_CONFIG_NAME
+	default "gxp"
+
+config SYS_TEXT_BASE
+	default 0x50000000
diff --git a/board/hpe/gxp/Makefile b/board/hpe/gxp/Makefile
new file mode 100644
index 0000000..775d6bf
--- /dev/null
+++ b/board/hpe/gxp/Makefile
@@ -0,0 +1 @@
+obj-y += gxp_board.o
diff --git a/board/hpe/gxp/gxp.env b/board/hpe/gxp/gxp.env
new file mode 100644
index 0000000..4760bf1
--- /dev/null
+++ b/board/hpe/gxp/gxp.env
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+recover_file=openbmc-hpe-recovery-image.mtd
+recover_cmd=usb start; mw.b 0xD100000D 0x40;
+	if fatload usb 0 0x50000000 $recover_file 0x4C0000 0x80000; then
+		setenv bootargs console=ttyS0,115200 recovery;
+		setenv force_recovery;
+		saveenv;
+		bootm  0x50000000;
+	else
+		while itest 0 < 1; do
+			mw.b 0xd1000005 0xc0;
+			sleep .1;
+		mw.b 0xd1000005 0x00;
+		sleep .1;
+		done;
+	fi;
+	reset;
+spiboot=if itest.b *0xD10000B2 == 6; then
+		run recover_cmd;
+	fi;
+	if printenv force_recovery; then
+		run recover_cmd;
+	else
+		bootm 0xfc080000;
+		run recover_cmd;
+	fi;
diff --git a/board/hpe/gxp/gxp_board.c b/board/hpe/gxp/gxp_board.c
new file mode 100644
index 0000000..d94d9b8
--- /dev/null
+++ b/board/hpe/gxp/gxp_board.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GXP timer driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <nick.hawkins@hpe.com>
+ * Author: Jean-Marie Verdun <verdun@hpe.com>
+ */
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ECHI_CMD 0xcefe0010
+
+int board_init(void)
+{
+	writel(0x00080002, ECHI_CMD);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (IS_ENABLED(CONFIG_TARGET_GXP)) {
+		if (IS_ENABLED(CONFIG_GXP_ECC)) {
+			/* 0x0f800000 */
+			gd->ram_size = SZ_128M + SZ_64M + SZ_32M + SZ_16M + SZ_8M;
+		} else {
+			/* 0x1f000000 */
+			gd->ram_size = SZ_256M + SZ_128M + SZ_64M + SZ_32M + SZ_16M;
+		}
+
+		if (IS_ENABLED(CONFIG_GXP_VROM_64MB)) {
+			if (IS_ENABLED(CONFIG_GXP_ECC)) {
+				/* 0x0c000000 */
+				gd->ram_size = SZ_128M + SZ_64M;
+			} else {
+				/* 0x18000000 */
+				gd->ram_size = SZ_256M + SZ_128M;
+			}
+		}
+
+		if (IS_ENABLED(CONFIG_GXP_VROM_32MB)) {
+			if (IS_ENABLED(CONFIG_GXP_ECC)) {
+				/* 0x0e000000 */
+				gd->ram_size = SZ_128M + SZ_64M + SZ_32M;
+			} else {
+				/* 0x1c000000 */
+				gd->ram_size = SZ_256M + SZ_128M + SZ_64M;
+			}
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_TARGET_GXP2)) {
+		/* 0x1b200000 */
+		gd->ram_size = SZ_256M + SZ_128M + SZ_32M + SZ_16M + SZ_2M;
+		if (IS_ENABLED(CONFIG_GXP_VROM_64MB)) {
+			/* 0x14000000 */
+			gd->ram_size = SZ_256M + SZ_64M;
+		}
+
+		if (IS_ENABLED(CONFIG_GXP_VROM_32MB)) {
+			/* 0x18000000 */
+			gd->ram_size = SZ_256M + SZ_128M;
+		}
+	}
+
+	return 0;
+}
+
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index 863c07d..f22faee 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -11,6 +11,9 @@ if VENDOR_KM
 
 menu "KM Board Setup"
 
+config HUSH_INIT_VAR
+	def_bool y
+
 config KM_PNVRAM
 	hex "Pseudo RAM"
 	default 0x80000
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index ecc8c78..8a0b175 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -102,8 +102,10 @@ int misc_init_r(void)
 int last_stage_init(void)
 {
 #if defined(CONFIG_TARGET_KMCOGE5NE)
-	struct bfticu_iomap *base =
-		(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
+	/*
+	 * BFTIC3 on the local bus CS4
+	 */
+	struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000;
 	u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
 
 	if (dip_switch != 0) {
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index 5a51372..09f8135 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -35,8 +35,6 @@ enum {
 
 #define GPIO_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 #define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 
 #define TOUCH_RESET_GPIO	IMX_GPIO_NR(3, 23)
 
@@ -54,15 +52,6 @@ static iomux_v3_cfg_t const touch_gpio[] = {
 	IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
 };
 
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	switch (boot_dev_spl) {
@@ -231,19 +220,6 @@ void spl_board_init(void)
 		printf("Failed to find clock node. Check device tree\n");
 }
 
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-	return 0;
-}
-
 static int power_init_board(void)
 {
 	struct udevice *dev;
@@ -278,12 +254,8 @@ void board_init_f(ulong dummy)
 
 	init_uart_clk(2);
 
-	board_early_init_f();
-
 	timer_init();
 
-	preloader_console_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -293,6 +265,8 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	preloader_console_init();
+
 	enable_tzc380();
 
 	/* PMIC initialization */
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c
index 4142699..315d9f9 100644
--- a/board/kontron/sl28/ddr.c
+++ b/board/kontron/sl28/ddr.c
@@ -54,6 +54,9 @@ static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
 
 	.ddr_cdr1		= 0x80040000,
 	.ddr_cdr2		= 0x0000bc01,
+
+	/* Erratum A-009942, set optimal CPO value */
+	.debug[28]		= 0x00700040,
 };
 
 int fsl_initdram(void)
@@ -66,11 +69,17 @@ int fsl_initdram(void)
 		dram_size = 0x80000000;
 		ddr_cfg_regs.cs[1].bnds = 0;
 		ddr_cfg_regs.cs[1].config = 0;
-		ddr_cfg_regs.cs[1].config_2 = 0;
 		break;
 	case GPPORCR1_MEM_4GB_CS0_1:
 		dram_size = 0x100000000ULL;
 		break;
+	case GPPORCR1_MEM_8GB_CS0_1:
+		dram_size = 0x200000000ULL;
+		ddr_cfg_regs.cs[0].bnds = 0x000000ff;
+		ddr_cfg_regs.cs[0].config = 0x80044403;
+		ddr_cfg_regs.cs[1].bnds = 0x010001ff;
+		ddr_cfg_regs.cs[1].config = 0x80044403;
+		break;
 	case GPPORCR1_MEM_512MB_CS0:
 		dram_size = 0x20000000;
 		fallthrough; /* for now */
@@ -80,7 +89,6 @@ int fsl_initdram(void)
 	case GPPORCR1_MEM_4GB_CS0_2:
 		dram_size = 0x100000000ULL;
 		fallthrough; /* for now */
-	case GPPORCR1_MEM_8GB_CS0_1:
 	case GPPORCR1_MEM_8GB_CS0_1_2_3:
 		dram_size = 0x200000000ULL;
 		fallthrough; /* for now */
diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c
index 980ffef..8349260 100644
--- a/board/lego/ev3/legoev3.c
+++ b/board/lego/ev3/legoev3.c
@@ -27,6 +27,7 @@
 #include <hwconfig.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -57,6 +58,8 @@ const int lpsc_size = ARRAY_SIZE(lpsc);
  */
 static void setup_serial_number(void)
 {
+	struct udevice *idev, *ibus;
+	int ret;
 	u32 offset;
 	char serial_number[13];
 	u8 buf[6];
@@ -65,7 +68,15 @@ static void setup_serial_number(void)
 	if (env_get("serial#"))
 		return;
 
-	if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) {
+	ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &ibus);
+	if (ret)
+		return;
+
+	ret = dm_i2c_probe(ibus, EEPROM_I2C_ADDR, 0, &idev);
+	if (ret)
+		return;
+
+	if (dm_i2c_read(idev, EEPROM_REV_OFFSET, buf, 2)) {
 		printf("\nEEPROM revision read failed!\n");
 		return;
 	}
@@ -83,7 +94,7 @@ static void setup_serial_number(void)
 	/* EEPROM rev 3 has Bluetooth address where rev should be */
 	offset = (eeprom_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_BDADDR_OFFSET;
 
-	if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) {
+	if (dm_i2c_read(idev, offset, buf, 6)) {
 		printf("\nEEPROM serial read failed!\n");
 		return;
 	}
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index d54145e..d87ab6d 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -57,31 +57,6 @@ int board_fit_config_name_match(const char *name)
 	return 0;
 }
 
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-	return 0;
-}
-
 void board_init_f(ulong dummy)
 {
 	int ret;
@@ -90,10 +65,6 @@ void board_init_f(ulong dummy)
 
 	init_uart_clk(2);
 
-	board_early_init_f();
-
-	preloader_console_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -103,6 +74,8 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	preloader_console_init();
+
 	enable_tzc380();
 
 	/* DDR initialization */
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index 19c486e..faed6fc 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -89,31 +89,6 @@ int board_fit_config_name_match(const char *name)
 	return 0;
 }
 
-#define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
-	MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-	return 0;
-}
-
 void board_init_f(ulong dummy)
 {
 	int ret;
@@ -122,8 +97,6 @@ void board_init_f(ulong dummy)
 
 	init_uart_clk(0);
 
-	board_early_init_f();
-
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_early_init() failed: %d\n", ret);
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.env b/board/qualcomm/dragonboard410c/dragonboard410c.env
new file mode 100644
index 0000000..9d9a575
--- /dev/null
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.env
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* Does what recovery does */
+#define REFLASH(file, partnum) \
+part start mmc 0 partnum start && \
+part size mmc 0 partnum size && \
+tftp $loadaddr file &&  \
+mmc write $loadaddr $start $size &&
+
+reflash=
+mmc dev 0 &&
+usb start &&
+dhcp &&
+tftp $loadaddr dragonboard/rescue/gpt_both0.bin &&
+mmc write $loadaddr 0 43 &&
+mmc rescan &&
+REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)
+REFLASH(dragonboard/rescue/sbl1.mbn, 2)
+REFLASH(dragonboard/rescue/rpm.mbn, 3)
+REFLASH(dragonboard/rescue/tz.mbn, 4)
+REFLASH(dragonboard/rescue/hyp.mbn, 5)
+REFLASH(dragonboard/rescue/sec.dat, 6)
+REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)
+REFLASH(dragonboard/u-boot.img, 8)
+usb stop &&
+echo Reflash completed
+
+loadaddr=0x81000000
+initrd_high=0xffffffffffffffff
+linux_image=Image
+kernel_addr_r=0x81000000
+fdtfile=qcom/apq8016-sbc.dtb
+fdt_addr_r=0x83000000
+ramdisk_addr_r=0x84000000
+scriptaddr=0x90000000
+pxefile_addr_r=0x90100000
diff --git a/board/qualcomm/dragonboard820c/u-boot.lds b/board/qualcomm/dragonboard820c/u-boot.lds
index dcf8256..5251b59 100644
--- a/board/qualcomm/dragonboard820c/u-boot.lds
+++ b/board/qualcomm/dragonboard820c/u-boot.lds
@@ -49,8 +49,8 @@ SECTIONS
 	. = .;
 
 	. = ALIGN(8);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
 	}
 
 	. = ALIGN(8);
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index b43242f..5320c1f 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -112,10 +112,10 @@ int checkboard(void)
 }
 #endif
 
-#ifdef CONFIG_S5P_PA_SYSRAM
+#ifdef CONFIG_SMP_PEN_ADDR
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
-	writel(addr, CONFIG_S5P_PA_SYSRAM);
+	writel(addr, CONFIG_SMP_PEN_ADDR);
 
 	/* make sure this write is really executed */
 	__asm__ volatile ("dsb\n");
diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds
index 5b32f7f..73cd97a 100644
--- a/board/samsung/common/exynos-uboot-spl.lds
+++ b/board/samsung/common/exynos-uboot-spl.lds
@@ -32,8 +32,8 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 	. = ALIGN(4);
 
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
 	} >.sram
 	. = ALIGN(4);
 
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index d066876..24bf355 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -403,16 +403,6 @@ int exynos_early_init_f(void)
 	return 0;
 }
 
-void exynos_reset_lcd(void)
-{
-	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
-	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
-	udelay(10000);
-	gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
-	udelay(10000);
-	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
-}
-
 int lcd_power(void)
 {
 #if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
@@ -460,16 +450,3 @@ int mipi_power(void)
 #endif
 	return 0;
 }
-
-#ifdef CONFIG_LCD
-void exynos_lcd_misc_init(vidinfo_t *vid)
-{
-#ifdef CONFIG_TIZEN
-	get_tizen_logo_info(vid);
-#endif
-#ifdef CONFIG_S6E8AX0
-	s6e8ax0_init();
-	env_set("lcdinfo", "lcd=s6e8ax0");
-#endif
-}
-#endif
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index a03dc87..da7f0dc 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -302,39 +302,4 @@ int mipi_power(void)
 	return 0;
 }
 
-void exynos_lcd_power_on(void)
-{
-#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
-	struct pmic *p = pmic_get("MAX77686_PMIC");
-
-	/* LCD_2.2V_EN: GPC0[1] */
-	gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en");
-	gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP);
-	gpio_direction_output(EXYNOS4X12_GPIO_C01, 1);
-
-	/* LDO25 VCC_3.1V_LCD */
-	pmic_probe(p);
-	max77686_set_ldo_voltage(p, 25, 3100000);
-	max77686_set_ldo_mode(p, 25, OPMODE_LPM);
-#endif
-}
-
-void exynos_reset_lcd(void)
-{
-	/* reset lcd */
-	gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset");
-	gpio_direction_output(EXYNOS4X12_GPIO_F21, 0);
-	udelay(10);
-	gpio_set_value(EXYNOS4X12_GPIO_F21, 1);
-}
-
-void exynos_lcd_misc_init(vidinfo_t *vid)
-{
-#ifdef CONFIG_TIZEN
-	get_tizen_logo_info(vid);
-#endif
-#ifdef CONFIG_S6E8AX0
-	s6e8ax0_init();
-#endif
-}
 #endif /* LCD */
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 3764b54..1dde2f7 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -267,98 +267,6 @@ static int init_pmic_lcd(void)
 	return 0;
 }
 
-void exynos_cfg_lcd_gpio(void)
-{
-	unsigned int i, f3_end = 4;
-
-	for (i = 0; i < 8; i++) {
-		/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
-		gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
-		gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
-		gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
-		/* pull-up/down disable */
-		gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
-		gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
-		gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
-
-		/* drive strength to max (24bit) */
-		gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
-		gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
-		gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
-		gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
-		gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
-		gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
-	}
-
-	for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
-		/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
-		gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
-		/* pull-up/down disable */
-		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
-		/* drive strength to max (24bit) */
-		gpio_set_drv(i, S5P_GPIO_DRV_4X);
-		gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
-	}
-
-	/* gpio pad configuration for LCD reset. */
-	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
-	gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
-}
-
-int mipi_power(void)
-{
-	return 0;
-}
-
-void exynos_reset_lcd(void)
-{
-	gpio_set_value(EXYNOS4_GPIO_Y45, 1);
-	udelay(10000);
-	gpio_set_value(EXYNOS4_GPIO_Y45, 0);
-	udelay(10000);
-	gpio_set_value(EXYNOS4_GPIO_Y45, 1);
-	udelay(100);
-}
-
-void exynos_lcd_power_on(void)
-{
-	struct udevice *dev;
-	int ret;
-	u8 reg;
-
-	ret = pmic_get("max8998-pmic", &dev);
-	if (ret) {
-		puts("Failed to get MAX8998!\n");
-		return;
-	}
-
-	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
-	reg |= MAX8998_LDO17;
-	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
-	if (ret) {
-		puts("MAX8998 LDO setting error\n");
-		return;
-	}
-
-	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
-	reg |= MAX8998_LDO7;
-	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
-	if (ret) {
-		puts("MAX8998 LDO setting error\n");
-		return;
-	}
-}
-
-void exynos_cfg_ldo(void)
-{
-	ld9040_cfg_ldo();
-}
-
-void exynos_enable_ldo(unsigned int onoff)
-{
-	ld9040_enable_ldo(onoff);
-}
-
 int exynos_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
@@ -390,18 +298,3 @@ int exynos_init(void)
 
 	return 0;
 }
-
-#ifdef CONFIG_LCD
-void exynos_lcd_misc_init(vidinfo_t *vid)
-{
-#ifdef CONFIG_TIZEN
-	get_tizen_logo_info(vid);
-#endif
-
-	/* for LD9040. */
-	vid->pclk_name = 1;	/* MPLL */
-	vid->sclk_div = 1;
-
-	env_set("lcdinfo", "lcd=ld9040");
-}
-#endif
diff --git a/board/sandbox/sandbox.env b/board/sandbox/sandbox.env
index b4c0463..a2c1970 100644
--- a/board/sandbox/sandbox.env
+++ b/board/sandbox/sandbox.env
@@ -6,10 +6,6 @@ stdout=serial,vidconsole
 stderr=serial,vidconsole
 
 ethaddr=02:00:11:22:33:44
-eth2addr=02:00:11:22:33:48
-eth3addr=02:00:11:22:33:45
-eth4addr=02:00:11:22:33:48
-eth5addr=02:00:11:22:33:46
 eth6addr=02:00:11:22:33:47
 ipaddr=192.0.2.1
 
diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig
new file mode 100644
index 0000000..131439f
--- /dev/null
+++ b/board/siemens/common/Kconfig
@@ -0,0 +1,2 @@
+config FACTORYSET
+	bool
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 3430a1e..27aad4e 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -59,7 +59,8 @@ int checkboard (void)
 		f = get_board_sys_clk();
 	} else {
 		src = "PCI_CLK";
-		f = CONFIG_PCI_CLK_FREQ;
+		/* PCI is clocked by the external source at 33 MHz */
+		f = 33000000;
 	}
 	printf ("PCI1:  32 bit, %d MHz (%s)\n",	f/1000000, src);
 #else
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index 5fb1be2..d52dce4 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -202,18 +202,4 @@ void stpmic1_init(u32 voltage_mv)
 			STPMIC1_BUCKS_MRST_CR,
 			STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
 			STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
-
-	/* Check if debug is enabled to program PMIC according to the bit */
-	if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) {
-		log_info("Keep debug unit ON\n");
-
-		pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
-				STPMIC1_MRST_BUCK_DEBUG,
-				STPMIC1_MRST_BUCK_DEBUG);
-
-		if (STPMIC1_MRST_LDO_DEBUG)
-			pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR,
-					STPMIC1_MRST_LDO_DEBUG,
-					STPMIC1_MRST_LDO_DEBUG);
-	}
 }
diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig
index 89e97ae..6ab8f80 100644
--- a/board/st/stm32mp1/Kconfig
+++ b/board/st/stm32mp1/Kconfig
@@ -11,3 +11,18 @@ config SYS_CONFIG_NAME
 
 source "board/st/common/Kconfig"
 endif
+
+if TARGET_ST_STM32MP13x
+
+config SYS_BOARD
+	default "stm32mp1"
+
+config SYS_VENDOR
+	default "st"
+
+config SYS_CONFIG_NAME
+	default "stm32mp13_st_common"
+
+source "board/st/common/Kconfig"
+
+endif
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
index 6451195..d5a09cd 100644
--- a/board/st/stm32mp1/MAINTAINERS
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -3,10 +3,14 @@ M:	Patrick Delaunay <patrick.delaunay@foss.st.com>
 L:	uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
 T:	git https://source.denx.de/u-boot/custodians/u-boot-stm.git
 S:	Maintained
+F:	arch/arm/dts/stm32mp13*
 F:	arch/arm/dts/stm32mp15*
 F:	board/st/stm32mp1/
+F:	configs/stm32mp13_defconfig
 F:	configs/stm32mp15_defconfig
 F:	configs/stm32mp15_basic_defconfig
 F:	configs/stm32mp15_trusted_defconfig
+F:	include/configs/stm32mp13_common.h
+F:	include/configs/stm32mp13_st_common.h
 F:	include/configs/stm32mp15_common.h
 F:	include/configs/stm32mp15_st_common.h
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 07b1a63..9496890 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -82,11 +82,6 @@
 #define SYSCFG_PMCSETR_ETH_SEL_RGMII	BIT(21)
 #define SYSCFG_PMCSETR_ETH_SEL_RMII	BIT(23)
 
-/*
- * Get a global data pointer
- */
-DECLARE_GLOBAL_DATA_PTR;
-
 #define USB_LOW_THRESHOLD_UV		200000
 #define USB_WARNING_LOW_THRESHOLD_UV	660000
 #define USB_START_LOW_THRESHOLD_UV	1230000
@@ -116,8 +111,8 @@ int checkboard(void)
 		mode = "basic";
 	}
 
-	fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
-				 &fdt_compat_len);
+	fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+					 &fdt_compat_len);
 
 	log_info("Board: stm32mp1 in %s mode (%s)\n", mode,
 		 fdt_compat && fdt_compat_len ? fdt_compat : "");
@@ -554,8 +549,7 @@ static void sysconf_init(void)
 	clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
 }
 
-/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
-static int dk2_i2c1_fix(void)
+static int board_stm32mp15x_dk2_init(void)
 {
 	ofnode node;
 	struct gpio_desc hdmi, audio;
@@ -564,6 +558,7 @@ static int dk2_i2c1_fix(void)
 	if (!IS_ENABLED(CONFIG_DM_REGULATOR))
 		return -ENODEV;
 
+	/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
 	node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
 	if (!ofnode_valid(node)) {
 		log_debug("no hdmi-transmitter@39 ?\n");
@@ -611,7 +606,7 @@ error:
 	return ret;
 }
 
-static bool board_is_dk2(void)
+static bool board_is_stm32mp15x_dk2(void)
 {
 	if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
 	    of_machine_is_compatible("st,stm32mp157c-dk2"))
@@ -620,7 +615,7 @@ static bool board_is_dk2(void)
 	return false;
 }
 
-static bool board_is_ev1(void)
+static bool board_is_stm32mp15x_ev1(void)
 {
 	if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
 	    (of_machine_is_compatible("st,stm32mp157a-ev1") ||
@@ -644,7 +639,7 @@ U_BOOT_DRIVER(goodix) = {
 	.of_match	= goodix_ids,
 };
 
-static void board_ev1_init(void)
+static void board_stm32mp15x_ev1_init(void)
 {
 	struct udevice *dev;
 
@@ -657,11 +652,11 @@ int board_init(void)
 {
 	board_key_check();
 
-	if (board_is_ev1())
-		board_ev1_init();
+	if (board_is_stm32mp15x_ev1())
+		board_stm32mp15x_ev1_init();
 
-	if (board_is_dk2())
-		dk2_i2c1_fix();
+	if (board_is_stm32mp15x_dk2())
+		board_stm32mp15x_dk2_init();
 
 	if (IS_ENABLED(CONFIG_DM_REGULATOR))
 		regulators_enable_boot_on(_DEBUG);
@@ -690,8 +685,8 @@ int board_late_init(void)
 	int buf_len;
 
 	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
-		fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
-					 &fdt_compat_len);
+		fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+						 &fdt_compat_len);
 		if (fdt_compat && fdt_compat_len) {
 			if (strncmp(fdt_compat, "st,", 3) != 0) {
 				env_set("board_name", fdt_compat);
diff --git a/board/synopsys/iot_devkit/u-boot.lds b/board/synopsys/iot_devkit/u-boot.lds
index d083168..e82e498 100644
--- a/board/synopsys/iot_devkit/u-boot.lds
+++ b/board/synopsys/iot_devkit/u-boot.lds
@@ -5,6 +5,7 @@
  */
 
 #include <config.h>
+#include <system-constants.h>
 
 MEMORY {
 	ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
@@ -39,8 +40,8 @@ SECTIONS
 	} > ROM
 
 	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
 
 		/* Mark RAM's LMA */
 		. = ALIGN(4);
diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig
index 4abcdb3..49d0274 100644
--- a/board/sysam/stmark2/Kconfig
+++ b/board/sysam/stmark2/Kconfig
@@ -3,6 +3,9 @@ if TARGET_STMARK2
 config CF_SBF
 	def_bool y
 
+config EXTRA_CLOCK
+	def_bool y
+
 config SYS_INPUT_CLKSRC
 	hex
 	default 30000000
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
index 03c1d5f..087dee8 100644
--- a/board/ti/am335x/u-boot.lds
+++ b/board/ti/am335x/u-boot.lds
@@ -72,8 +72,8 @@ SECTIONS
 	. = .;
 
 	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
 	}
 
 	. = ALIGN(4);
diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig
new file mode 100644
index 0000000..87fed44
--- /dev/null
+++ b/board/ti/am62x/Kconfig
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+#	Suman Anna <s-anna@ti.com>
+
+choice
+	prompt "TI K3 AM62x based boards"
+	optional
+
+config TARGET_AM625_A53_EVM
+	bool "TI K3 based AM625 EVM running on A53"
+	select ARM64
+	select SOC_K3_AM625
+
+config TARGET_AM625_R5_EVM
+	bool "TI K3 based AM625 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select SOC_K3_AM625
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_AM625_A53_EVM
+
+config SYS_BOARD
+       default "am62x"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "am62x_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM625_R5_EVM
+
+config SYS_BOARD
+       default "am62x"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "am62x_evm"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS
new file mode 100644
index 0000000..105e741
--- /dev/null
+++ b/board/ti/am62x/MAINTAINERS
@@ -0,0 +1,8 @@
+AM62x BOARD
+M:	Dave Gerlach <d-gerlach@ti.com>
+M:	Tom Rini <trini@konsulko.com>
+S:	Maintained
+F:	board/ti/am62x/
+F:	include/configs/am62x_evm.h
+F:	configs/am62x_evm_r5_defconfig
+F:	configs/am62x_evm_a53_defconfig
diff --git a/board/ti/am62x/Makefile b/board/ti/am62x/Makefile
new file mode 100644
index 0000000..f4c35ed
--- /dev/null
+++ b/board/ti/am62x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+#	Suman Anna <s-anna@ti.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evm.o
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
new file mode 100644
index 0000000..d65ee1d
--- /dev/null
+++ b/board/ti/am62x/evm.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM62x platforms
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ *	Suman Anna <s-anna@ti.com>
+ *
+ */
+
+#include <asm/io.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <k3-ddrss.h>
+#include <fdt_support.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <env.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_K3_AM64_DDRSS)
+static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
+{
+	struct udevice *dev;
+	int ret;
+
+	dram_init_banksize();
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret)
+		panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
+
+	ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
+	if (ret)
+		printf("Error fixing up ddr node for ECC use! %d\n", ret);
+}
+#else
+static void fixup_memory_node(struct spl_image_info *spl_image)
+{
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	int bank;
+	int ret;
+
+	dram_init();
+	dram_init_banksize();
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] =  gd->bd->bi_dram[bank].start;
+		size[bank] = gd->bd->bi_dram[bank].size;
+	}
+
+	/* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
+	ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
+				     CONFIG_NR_DRAM_BANKS);
+	if (ret)
+		printf("Error fixing up memory node! %d\n", ret);
+}
+#endif
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+#if defined(CONFIG_K3_AM64_DDRSS)
+	fixup_ddr_driver_for_ecc(spl_image);
+#else
+	fixup_memory_node(spl_image);
+#endif
+}
+#endif
diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig
index d4ec759..8036947 100644
--- a/board/ti/am64x/Kconfig
+++ b/board/ti/am64x/Kconfig
@@ -54,9 +54,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
        default "am64x_evm"
 
-config SPL_LDSCRIPT
-	default "arch/arm/mach-omap2/u-boot-spl.lds"
-
 source "board/ti/common/Kconfig"
 
 endif
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index 47b41cd..16a7476 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -53,9 +53,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
        default "am65x_evm"
 
-config SPL_LDSCRIPT
-	default "arch/arm/mach-omap2/u-boot-spl.lds"
-
 source "board/ti/common/Kconfig"
 
 endif
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index de92eb0..ed34991 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -86,7 +86,7 @@ __weak void gpi2c_init(void)
 static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 					    u32 header, u32 size, uint8_t *ep)
 {
-	u32 hdr_read;
+	u32 hdr_read = 0xdeadbeef;
 	int rc;
 
 #if CONFIG_IS_ENABLED(DM_I2C)
@@ -103,21 +103,25 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 	/*
 	 * Read the header first then only read the other contents.
 	 */
-	rc = i2c_set_chip_offset_len(dev, 2);
+	rc = i2c_set_chip_offset_len(dev, 1);
 	if (rc)
 		return rc;
 
-	rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
-	if (rc)
-		return rc;
+	/*
+	 * Skip checking result here since this could be a valid i2c read fail
+	 * on some boards that use 2 byte addressing.
+	 * We must allow for fall through to check the data if 2 byte
+	 * addressing works
+	 */
+	(void)dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
 
 	/* Corrupted data??? */
 	if (hdr_read != header) {
 		/*
 		 * read the eeprom header using i2c again, but use only a
-		 * 1 byte address (some legacy boards need this..)
+		 * 2 byte address (some newer boards need this..)
 		 */
-		rc = i2c_set_chip_offset_len(dev, 1);
+		rc = i2c_set_chip_offset_len(dev, 2);
 		if (rc)
 			return rc;
 
@@ -142,19 +146,23 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 	/*
 	 * Read the header first then only read the other contents.
 	 */
-	byte = 2;
+	byte = 1;
 
-	rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
-	if (rc)
-		return rc;
+	/*
+	 * Skip checking result here since this could be a valid i2c read fail
+	 * on some boards that use 2 byte addressing.
+	 * We must allow for fall through to check the data if 2 byte
+	 * addressing works
+	 */
+	(void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
 
 	/* Corrupted data??? */
 	if (hdr_read != header) {
 		/*
 		 * read the eeprom header using i2c again, but use only a
-		 * 1 byte address (some legacy boards need this..)
+		 * 2 byte address (some newer boards need this..)
 		 */
-		byte = 1;
+		byte = 2;
 		rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read,
 			      4);
 		if (rc)
@@ -434,6 +442,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
 	struct ti_am6_eeprom_record_board_id board_id;
 	struct ti_am6_eeprom_record record;
 	int rc;
+	int consecutive_bad_records = 0;
 
 	/* Initialize with a known bad marker for i2c fails.. */
 	memset(ep, 0, sizeof(*ep));
@@ -470,7 +479,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
 	 */
 	eeprom_addr = sizeof(board_id);
 
-	while (true) {
+	while (consecutive_bad_records < 10) {
 		rc = dm_i2c_read(dev, eeprom_addr, (uint8_t *)&record.header,
 				 sizeof(record.header));
 		if (rc)
@@ -506,6 +515,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
 				pr_err("%s: EEPROM parsing error!\n", __func__);
 				return rc;
 			}
+			consecutive_bad_records = 0;
 		} else {
 			/*
 			 * We may get here in case of larger records which
@@ -513,6 +523,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
 			 */
 			pr_err("%s: Ignoring record id %u\n", __func__,
 			       record.header.id);
+			consecutive_bad_records++;
 		}
 
 		eeprom_addr += record.header.len;
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 96434b3..39b5c706 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -159,6 +159,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 int misc_init_r(void)
 {
 	twl4030_power_init();
+	twl4030_power_mmc_init(0);
 
 #if defined(CONFIG_SMC911X)
 	setup_net_chip();
@@ -247,10 +248,3 @@ static void reset_net_chip(void)
 	gpio_set_value(rst_gpio, 1);
 }
 #endif /* CONFIG_SMC911X */
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
-	twl4030_power_mmc_init(0);
-}
-#endif /* CONFIG_MMC */
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index c28752a..d19d30d 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -75,9 +75,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
        default "j721e_evm"
 
-config SPL_LDSCRIPT
-	default "arch/arm/mach-omap2/u-boot-spl.lds"
-
 source "board/ti/common/Kconfig"
 
 endif
@@ -108,9 +105,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
        default "j721e_evm"
 
-config SPL_LDSCRIPT
-	default "arch/arm/mach-omap2/u-boot-spl.lds"
-
 source "board/ti/common/Kconfig"
 
 endif
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index e6ff54c..5d09004 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -109,11 +109,12 @@ int board_fit_config_name_match(const char *name)
 static void __maybe_unused detect_enable_hyperflash(void *blob)
 {
 	struct gpio_desc desc = {0};
+	char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
 
-	if (dm_gpio_lookup_name("6", &desc))
+	if (dm_gpio_lookup_name(hypermux_sel_gpio, &desc))
 		return;
 
-	if (dm_gpio_request(&desc, "6"))
+	if (dm_gpio_request(&desc, hypermux_sel_gpio))
 		return;
 
 	if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN))
@@ -132,7 +133,8 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
 }
 #endif
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \
+					defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM))
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
 	detect_enable_hyperflash(spl_image->fdt_addr);
@@ -380,19 +382,25 @@ void configure_serdes_torrent(void)
 	ret = uclass_get_device_by_driver(UCLASS_PHY,
 					  DM_DRIVER_GET(torrent_phy_provider),
 					  &dev);
-	if (ret)
+	if (ret) {
 		printf("Torrent init failed:%d\n", ret);
+		return;
+	}
 
 	serdes.dev = dev;
 	serdes.id = 0;
 
 	ret = generic_phy_init(&serdes);
-	if (ret)
-		printf("phy_init failed!!\n");
+	if (ret) {
+		printf("phy_init failed!!: %d\n", ret);
+		return;
+	}
 
 	ret = generic_phy_power_on(&serdes);
-	if (ret)
-		printf("phy_power_on failed !!\n");
+	if (ret) {
+		printf("phy_power_on failed!!: %d\n", ret);
+		return;
+	}
 }
 
 void configure_serdes_sierra(void)
@@ -408,21 +416,27 @@ void configure_serdes_sierra(void)
 	ret = uclass_get_device_by_driver(UCLASS_MISC,
 					  DM_DRIVER_GET(sierra_phy_provider),
 					  &dev);
-	if (ret)
+	if (ret) {
 		printf("Sierra init failed:%d\n", ret);
+		return;
+	}
 
 	count = device_get_child_count(dev);
 	for (i = 0; i < count; i++) {
 		ret = device_get_child(dev, i, &link_dev);
-		if (ret)
-			printf("probe of sierra child node %d failed\n", i);
+		if (ret) {
+			printf("probe of sierra child node %d failed: %d\n", i, ret);
+			return;
+		}
 		if (link_dev->driver->id == UCLASS_PHY) {
 			link.dev = link_dev;
 			link.id = link_count++;
 
 			ret = generic_phy_power_on(&link);
-			if (ret)
-				printf("phy_power_on failed !!\n");
+			if (ret) {
+				printf("phy_power_on failed!!: %d\n", ret);
+				return;
+			}
 		}
 	}
 }
@@ -490,6 +504,41 @@ int board_late_init(void)
 }
 #endif
 
+static int __maybe_unused detect_SW3_1_state(void)
+{
+	if (IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) {
+		struct gpio_desc desc = {0};
+		int ret;
+		char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
+
+		ret = dm_gpio_lookup_name(hypermux_sel_gpio, &desc);
+		if (ret) {
+			printf("error getting GPIO lookup name: %d\n", ret);
+			return ret;
+		}
+
+		ret = dm_gpio_request(&desc, hypermux_sel_gpio);
+		if (ret) {
+			printf("error requesting GPIO: %d\n", ret);
+			goto err_free_gpio;
+		}
+
+		ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
+		if (ret) {
+			printf("error setting direction flag of GPIO: %d\n", ret);
+			goto err_free_gpio;
+		}
+
+		ret = dm_gpio_get_value(&desc);
+		if (ret < 0)
+			printf("error getting value of GPIO: %d\n", ret);
+
+err_free_gpio:
+		dm_gpio_free(desc.dev, &desc);
+		return ret;
+	}
+}
+
 void spl_board_init(void)
 {
 #if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC)
@@ -522,4 +571,18 @@ void spl_board_init(void)
 			printf("ESM PMIC init failed: %d\n", ret);
 	}
 #endif
+	if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) &&
+	    IS_ENABLED(CONFIG_HBMC_AM654)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = detect_SW3_1_state();
+		if (ret == 1) {
+			ret = uclass_get_device_by_driver(UCLASS_MTD,
+							  DM_DRIVER_GET(hbmc_am654),
+							  &dev);
+			if (ret)
+				debug("Failed to probe hyperflash\n");
+		}
+	}
 }
diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig
index 2e115f1..6141798 100644
--- a/board/ti/j721s2/Kconfig
+++ b/board/ti/j721s2/Kconfig
@@ -55,9 +55,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
        default "j721s2_evm"
 
-config SPL_LDSCRIPT
-	default "arch/arm/mach-omap2/u-boot-spl.lds"
-
 source "board/ti/common/Kconfig"
 
 endif
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 6c8cf45..9305709 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -159,6 +159,42 @@ const char * const toradex_display_adapters[] = {
 	[159] = "Verdin DSI to LVDS Adapter",
 };
 
+const u32 toradex_ouis[] = {
+	[0] = 0x00142dUL,
+	[1] = 0x8c06cbUL,
+};
+
+static u32 get_serial_from_mac(struct toradex_eth_addr *eth_addr)
+{
+	int i;
+	u32 oui = ntohl(eth_addr->oui) >> 8;
+	u32 nic = ntohl(eth_addr->nic) >> 8;
+
+	for (i = 0; i < ARRAY_SIZE(toradex_ouis); i++) {
+		if (toradex_ouis[i] == oui)
+			break;
+	}
+
+	return (u32)((i << 24) + nic);
+}
+
+void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr)
+{
+	u8 oui_index = tdx_serial >> 24;
+	u32 nic = tdx_serial & GENMASK(23, 0);
+	u32 oui;
+
+	if (oui_index >= ARRAY_SIZE(toradex_ouis)) {
+		puts("Can't find OUI for this serial#\n");
+		oui_index = 0;
+	}
+
+	oui = toradex_ouis[oui_index];
+
+	eth_addr->oui = htonl(oui << 8);
+	eth_addr->nic = htonl(nic << 8);
+}
+
 #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
 static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
 {
@@ -331,8 +367,7 @@ int read_tdx_cfg_block(void)
 				memcpy(&tdx_eth_addr, config_block + offset,
 				       6);
 
-				/* NIC part of MAC address is serial number */
-				tdx_serial = ntohl(tdx_eth_addr.nic) >> 8;
+				tdx_serial = get_serial_from_mac(&tdx_eth_addr);
 				break;
 			case TAG_HW:
 				memcpy(&tdx_hw_tag, config_block + offset, 8);
@@ -354,6 +389,18 @@ out:
 	return ret;
 }
 
+static int parse_assembly_string(char *string_to_parse, u16 *assembly)
+{
+	if (string_to_parse[3] >= 'A' && string_to_parse[3] <= 'Z')
+		*assembly = string_to_parse[3] - 'A';
+	else if (string_to_parse[3] == '#')
+		*assembly = dectoul(&string_to_parse[4], NULL);
+	else
+		return -EINVAL;
+
+	return 0;
+}
+
 static int get_cfgblock_interactive(void)
 {
 	char message[CONFIG_SYS_CBSIZE];
@@ -362,6 +409,7 @@ static int get_cfgblock_interactive(void)
 	char wb = 'n';
 	char mem8g = 'n';
 	int len = 0;
+	int ret = 0;
 
 	/* Unknown module by default */
 	tdx_hw_tag.prodid = 0;
@@ -545,13 +593,18 @@ static int get_cfgblock_interactive(void)
 	}
 
 	while (len < 4) {
-		sprintf(message, "Enter the module version (e.g. V1.1B): V");
+		sprintf(message, "Enter the module version (e.g. V1.1B or V1.1#26): V");
 		len = cli_readline(message);
 	}
 
 	tdx_hw_tag.ver_major = console_buffer[0] - '0';
 	tdx_hw_tag.ver_minor = console_buffer[2] - '0';
-	tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
+
+	ret = parse_assembly_string(console_buffer, &tdx_hw_tag.ver_assembly);
+	if (ret) {
+		printf("Parsing module version failed\n");
+		return ret;
+	}
 
 	while (len < 8) {
 		sprintf(message, "Enter module serial number: ");
@@ -754,6 +807,7 @@ static int get_cfgblock_carrier_interactive(void)
 {
 	char message[CONFIG_SYS_CBSIZE];
 	int len;
+	int ret = 0;
 
 	printf("Supported carrier boards:\n");
 	printf("CARRIER BOARD NAME\t\t [ID]\n");
@@ -767,13 +821,18 @@ static int get_cfgblock_carrier_interactive(void)
 	tdx_car_hw_tag.prodid = dectoul(console_buffer, NULL);
 
 	do {
-		sprintf(message, "Enter carrier board version (e.g. V1.1B): V");
+		sprintf(message, "Enter carrier board version (e.g. V1.1B or V1.1#26): V");
 		len = cli_readline(message);
 	} while (len < 4);
 
 	tdx_car_hw_tag.ver_major = console_buffer[0] - '0';
 	tdx_car_hw_tag.ver_minor = console_buffer[2] - '0';
-	tdx_car_hw_tag.ver_assembly = console_buffer[3] - 'A';
+
+	ret = parse_assembly_string(console_buffer, &tdx_car_hw_tag.ver_assembly);
+	if (ret) {
+		printf("Parsing module version failed\n");
+		return ret;
+	}
 
 	while (len < 8) {
 		sprintf(message, "Enter carrier board serial number: ");
@@ -950,8 +1009,7 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc,
 	}
 
 	/* Convert serial number to MAC address (the storage format) */
-	tdx_eth_addr.oui = htonl(0x00142dUL << 8);
-	tdx_eth_addr.nic = htonl(tdx_serial << 8);
+	get_mac_from_serial(tdx_serial, &tdx_eth_addr);
 
 	/* Valid Tag */
 	write_tag(config_block, &offset, TAG_VALID, NULL, 0);
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 43e662e..1790698 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -114,4 +114,6 @@ int read_tdx_cfg_block_carrier(void);
 
 int try_migrate_tdx_cfg_block_carrier(void);
 
+void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr);
+
 #endif /* _TDX_CFG_BLOCK_H */
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index 9db4553..3798bf9 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -20,15 +20,17 @@
 #include <asm/setup.h>
 #include "tdx-common.h"
 
-#define TORADEX_OUI 0x00142dUL
+#define SERIAL_STR_LEN 8
+#define MODULE_VER_STR_LEN 4 // V1.1
+#define MODULE_REV_STR_LEN 3 // [A-Z] or #[26-99]
 
 #ifdef CONFIG_TDX_CFG_BLOCK
-static char tdx_serial_str[9];
-static char tdx_board_rev_str[6];
+static char tdx_serial_str[SERIAL_STR_LEN + 1];
+static char tdx_board_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1];
 
 #ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
-static char tdx_car_serial_str[9];
-static char tdx_car_rev_str[6];
+static char tdx_car_serial_str[SERIAL_STR_LEN + 1];
+static char tdx_car_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1];
 static char *tdx_carrier_board_name;
 #endif
 
@@ -79,21 +81,37 @@ void get_board_serial(struct tag_serialnr *serialnr)
 }
 #endif /* CONFIG_SERIAL_TAG */
 
+static const char *get_board_assembly(u16 ver_assembly)
+{
+	static char ver_name[MODULE_REV_STR_LEN + 1];
+
+	if (ver_assembly < 26) {
+		ver_name[0] = (char)ver_assembly + 'A';
+		ver_name[1] = '\0';
+	} else {
+		snprintf(ver_name, sizeof(ver_name),
+			 "#%u", ver_assembly);
+	}
+
+	return ver_name;
+}
+
 int show_board_info(void)
 {
 	unsigned char ethaddr[6];
 
 	if (read_tdx_cfg_block()) {
 		printf("MISSING TORADEX CONFIG BLOCK\n");
-		tdx_eth_addr.oui = htonl(TORADEX_OUI << 8);
-		tdx_eth_addr.nic = htonl(tdx_serial << 8);
+		get_mac_from_serial(tdx_serial, &tdx_eth_addr);
 		checkboard();
 	} else {
-		sprintf(tdx_serial_str, "%08u", tdx_serial);
-		sprintf(tdx_board_rev_str, "V%1d.%1d%c",
-			tdx_hw_tag.ver_major,
-			tdx_hw_tag.ver_minor,
-			(char)tdx_hw_tag.ver_assembly + 'A');
+		snprintf(tdx_serial_str, sizeof(tdx_serial_str),
+			 "%08u", tdx_serial);
+		snprintf(tdx_board_rev_str, sizeof(tdx_board_rev_str),
+			 "V%1d.%1d%s",
+			 tdx_hw_tag.ver_major,
+			 tdx_hw_tag.ver_minor,
+			 get_board_assembly(tdx_hw_tag.ver_assembly));
 
 		env_set("serial#", tdx_serial_str);
 
@@ -109,12 +127,13 @@ int show_board_info(void)
 			tdx_carrier_board_name = (char *)
 				toradex_carrier_boards[tdx_car_hw_tag.prodid];
 
-			sprintf(tdx_car_serial_str, "%08u", tdx_car_serial);
-			sprintf(tdx_car_rev_str, "V%1d.%1d%c",
-				tdx_car_hw_tag.ver_major,
-				tdx_car_hw_tag.ver_minor,
-				(char)tdx_car_hw_tag.ver_assembly +
-				'A');
+			snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str),
+				 "%08u", tdx_car_serial);
+			snprintf(tdx_car_rev_str, sizeof(tdx_car_rev_str),
+				 "V%1d.%1d%s",
+				 tdx_car_hw_tag.ver_major,
+				 tdx_car_hw_tag.ver_minor,
+				 get_board_assembly(tdx_car_hw_tag.ver_assembly));
 
 			env_set("carrier_serial#", tdx_car_serial_str);
 			printf("Carrier: Toradex %s %s, Serial# %s\n",
@@ -170,7 +189,7 @@ int ft_common_board_setup(void *blob, struct bd_info *bd)
 	if (tdx_hw_tag.ver_major) {
 		char prod_id[5];
 
-		sprintf(prod_id, "%04u", tdx_hw_tag.prodid);
+		snprintf(prod_id, sizeof(prod_id), "%04u", tdx_hw_tag.prodid);
 		fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5);
 
 		fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str,
diff --git a/board/variscite/imx8mn_var_som/Kconfig b/board/variscite/imx8mn_var_som/Kconfig
index cfe6fc8..9a4003a 100644
--- a/board/variscite/imx8mn_var_som/Kconfig
+++ b/board/variscite/imx8mn_var_som/Kconfig
@@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c
index 32703c5..41e7050 100644
--- a/board/variscite/imx8mn_var_som/spl.c
+++ b/board/variscite/imx8mn_var_som/spl.c
@@ -40,26 +40,8 @@ void spl_board_init(void)
 		puts("Failed to find clock node. Check device tree\n");
 }
 
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t uart_pads[] = {
-	IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static const iomux_v3_cfg_t wdog_pads[] = {
-	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
 int board_early_init_f(void)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 	init_uart_clk(3);
 
 	return 0;
@@ -78,14 +60,14 @@ void board_init_f(ulong dummy)
 
 	timer_init();
 
-	preloader_console_init();
-
 	ret = spl_init();
 	if (ret) {
 		debug("spl_init() failed: %d\n", ret);
 		hang();
 	}
 
+	preloader_console_init();
+
 	/* DDR initialization */
 	spl_dram_init();
 
diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds
index 315ba5b..cb2ee67 100644
--- a/board/vscom/baltos/u-boot.lds
+++ b/board/vscom/baltos/u-boot.lds
@@ -53,8 +53,8 @@ SECTIONS
 	. = .;
 
 	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
 	}
 
 	. = ALIGN(4);
diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile
index 2120284..cdc3c96 100644
--- a/board/xilinx/common/Makefile
+++ b/board/xilinx/common/Makefile
@@ -5,6 +5,9 @@
 #
 
 obj-y	+= board.o
+ifndef CONFIG_ARCH_ZYNQ
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
+endif
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_FRU) += fru.o fru_ops.o
 endif
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 629a6ee..5f2afb9 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -485,31 +485,6 @@ int __maybe_unused board_fit_config_name_match(const char *name)
 	return -1;
 }
 
-#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_ARCH_ZYNQ)
-int print_cpuinfo(void)
-{
-	struct udevice *soc;
-	char name[SOC_MAX_STR_SIZE];
-	int ret;
-
-	ret = soc_get(&soc);
-	if (ret) {
-		printf("CPU:   UNKNOWN\n");
-		return 0;
-	}
-
-	ret = soc_get_family(soc, name, SOC_MAX_STR_SIZE);
-	if (ret)
-		printf("CPU:   %s\n", name);
-
-	ret = soc_get_revision(soc, name, SOC_MAX_STR_SIZE);
-	if (ret)
-		printf("Silicon: %s\n", name);
-
-	return 0;
-}
-#endif
-
 #if CONFIG_IS_ENABLED(DTB_RESELECT)
 #define MAX_NAME_LENGTH	50
 
diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c
new file mode 100644
index 0000000..4a863d0
--- /dev/null
+++ b/board/xilinx/common/cpu-info.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 - 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <soc.h>
+
+int print_cpuinfo(void)
+{
+	struct udevice *soc;
+	char name[SOC_MAX_STR_SIZE];
+	int ret;
+
+	ret = soc_get(&soc);
+	if (ret) {
+		printf("CPU:   UNKNOWN\n");
+		return 0;
+	}
+
+	ret = soc_get_family(soc, name, SOC_MAX_STR_SIZE);
+	if (ret)
+		printf("CPU:   %s\n", name);
+
+	ret = soc_get_revision(soc, name, SOC_MAX_STR_SIZE);
+	if (ret)
+		printf("Silicon: %s\n", name);
+
+	ret = soc_get_machine(soc, name, SOC_MAX_STR_SIZE);
+	if (ret)
+		printf("Chip:  %s\n", name);
+
+	return 0;
+}
diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index 117b476..dd5eace 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -38,6 +38,14 @@ config XILINX_MICROBLAZE0_HW_VER
 	string "Core version number"
 	default "7.10.d"
 
+config XILINX_MICROBLAZE0_FPGA_FAMILY
+	string "Targeted FPGA family"
+	default "virtex5"
+	help
+	  This option contains info about the target FPGA architecture
+	  (Zynq-7000, UltraScale+ Kintex, etc) that the MicroBlaze soft core is
+	  implemented on. It corresponds to the C_FAMILY hdl parameter.
+
 config XILINX_MICROBLAZE0_USR_EXCEP
 	bool "MicroBlaze user exception support"
 	default y
@@ -63,4 +71,50 @@ config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
 	  Memory address location of the exception vector table. It is
 	  configurable via the C_BASE_VECTORS hdl parameter.
 
+config XILINX_MICROBLAZE0_USE_WDC
+	bool "MicroBlaze wdc instruction support"
+	default y
+	help
+	  Enable this option if the MicroBlaze processor is configured with
+	  support for the "wdc" (Write to Data Cache) instruction.
+
+config SPL_XILINX_MICROBLAZE0_USE_WDC
+	bool
+	default XILINX_MICROBLAZE0_USE_WDC
+
+config XILINX_MICROBLAZE0_USE_WIC
+	bool "MicroBlaze wic instruction support"
+	default y
+	help
+	  Enable this option if the MicroBlaze processor is configured with
+	  support for the "wic" (Write to Instruction Cache) instruction.
+
+config SPL_XILINX_MICROBLAZE0_USE_WIC
+	bool
+	default XILINX_MICROBLAZE0_USE_WIC
+
+config XILINX_MICROBLAZE0_DCACHE_SIZE
+	int "Default data cache size"
+	default 32768
+	help
+	  This fallback size will be used when no dcache info can be found in
+	  the device tree, or when the data cache is flushed very early in the
+	  boot process, before device tree is available.
+
+config XILINX_MICROBLAZE0_ICACHE_SIZE
+	int "Default instruction cache size"
+	default 32768
+	help
+	  This fallback size will be used when no icache info can be found in
+	  the device tree, or when the instruction cache is flushed very early
+	  in the boot process, before device tree is available.
+
+config XILINX_MICROBLAZE0_PVR
+	bool "MicroBlaze PVR support"
+	help
+	  Enables helper functions and macros needed to manipulate PVR
+	  (Processor Version Register) data. Currently, only the microblaze
+	  UCLASS_CPU driver makes use of this feature to retrieve CPU info at
+	  runtime.
+
 endif
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index a88f5bb..81663e0 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -91,6 +91,23 @@ int board_early_init_r(void)
 	return 0;
 }
 
+unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+			 char *const argv[])
+{
+	int ret = 0;
+
+	if (current_el() > 1) {
+		smp_kick_all_cpus();
+		dcache_disable();
+		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
+				    ES_TO_AARCH64);
+	} else {
+		printf("FAIL: current EL is not above EL1\n");
+		ret = EINVAL;
+	}
+	return ret;
+}
+
 static u8 versal_get_bootmode(void)
 {
 	u8 bootmode;
diff --git a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c
index 40d9279..5ec3271 100644
--- a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c
@@ -6,879 +6,6 @@
 #include <asm/arch/psu_init_gpl.h>
 #include <xil_io.h>
 
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
-			   u32 lane2_protocol, u32 lane2_rate,
-			   u32 lane1_protocol, u32 lane1_rate,
-			   u32 lane0_protocol, u32 lane0_rate);
-
-static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly,
-		      int d_lock_cnt, int d_lfhf, int d_cp, int d_res);
-
-static unsigned long psu_pll_init_data(void)
-{
-	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
-	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
-	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
-	mask_poll(0xFF5E0040, 0x00000002U);
-	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
-	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
-	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
-	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
-	mask_poll(0xFF5E0040, 0x00000001U);
-	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
-	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
-	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
-	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000001U);
-	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
-	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
-	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
-	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000002U);
-	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
-	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
-	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
-	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000004U);
-	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_clock_init_data(void)
-{
-	psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
-	psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
-	psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
-	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
-	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
-	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
-	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
-	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
-	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
-	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
-	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
-	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
-	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
-	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
-	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
-	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
-	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
-	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
-	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
-	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
-	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
-	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_init_data(void)
-{
-	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
-	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
-	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
-	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
-	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
-	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
-	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
-	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
-	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
-	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
-	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
-	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
-	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
-	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
-	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
-	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
-	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
-	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
-	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
-	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
-	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
-	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
-	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
-	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
-	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U);
-	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
-	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
-	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
-	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
-	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
-	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
-	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
-	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
-	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
-	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
-	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
-	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
-	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
-	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
-	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
-	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
-	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
-	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
-	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
-	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
-	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
-	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
-	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
-	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
-	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
-	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
-	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
-	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
-	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
-	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
-	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
-	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
-	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
-	psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
-	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
-	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
-	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
-	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
-	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
-	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
-	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
-	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
-	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
-	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
-	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
-	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
-	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
-	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
-	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
-	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
-	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
-	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
-	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
-	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
-	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
-	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
-	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U);
-	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
-	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
-	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U);
-	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
-	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
-	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
-	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
-	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
-	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
-	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
-	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
-	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
-	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
-	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
-	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
-	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U);
-	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
-	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
-	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
-	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
-	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
-	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
-	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
-	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
-	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
-	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
-	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
-	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
-	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
-	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
-	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
-	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
-	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
-	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
-	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
-	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
-	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
-	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U);
-	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U);
-	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
-	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
-	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
-	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U);
-	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
-	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
-	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
-	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
-	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
-	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
-	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
-	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
-	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
-	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
-	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
-	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
-	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
-	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
-	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
-	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
-	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
-	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
-	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
-	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
-	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
-	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
-	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
-	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
-	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
-	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
-	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
-	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
-	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
-	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
-	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
-	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
-	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
-	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
-	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
-	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
-	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
-	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
-	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
-	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
-	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
-	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_qos_init_data(void)
-{
-	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_mio_init_data(void)
-{
-	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
-	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
-	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U);
-	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U);
-	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_peripherals_pre_init_data(void)
-{
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
-
-	return 1;
-}
-
-static unsigned long psu_peripherals_init_data(void)
-{
-	psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
-	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
-	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
-	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
-	psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U);
-	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
-	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
-	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
-	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
-	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
-	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
-	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
-	return 1;
-}
-
-static unsigned long psu_serdes_init_data(void)
-{
-	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
-	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
-	psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
-	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
-	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
-	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
-	psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
-	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
-
-	serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0);
-	psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U);
-	psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_resetout_init_data(void)
-{
-	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
-	mask_poll(0xFD4023E4, 0x00000010U);
-
-	return 1;
-}
-
-static unsigned long psu_resetin_init_data(void)
-{
-	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
-
-	return 1;
-}
-
-static unsigned long psu_afi_config(void)
-{
-	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
-	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
-	psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_phybringup_data(void)
-{
-	unsigned int regval = 0;
-
-	for (int tp = 0; tp < 20; tp++)
-		regval = Xil_In32(0xFD070018);
-	int cur_PLLCR0;
-
-	cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
-	int cur_DX8SL0PLLCR0;
-
-	cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
-	int cur_DX8SL1PLLCR0;
-
-	cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
-	int cur_DX8SL2PLLCR0;
-
-	cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
-	int cur_DX8SL3PLLCR0;
-
-	cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
-	int cur_DX8SL4PLLCR0;
-
-	cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
-	int cur_DX8SLBPLLCR0;
-
-	cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
-	Xil_Out32(0xFD080068, 0x02120000);
-	Xil_Out32(0xFD081404, 0x02120000);
-	Xil_Out32(0xFD081444, 0x02120000);
-	Xil_Out32(0xFD081484, 0x02120000);
-	Xil_Out32(0xFD0814C4, 0x02120000);
-	Xil_Out32(0xFD081504, 0x02120000);
-	Xil_Out32(0xFD0817C4, 0x02120000);
-	int cur_div2;
-
-	cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U;
-	int cur_fbdiv;
-
-	cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
-	dpll_prog(1, 49, 63, 625, 3, 3, 2);
-	for (int tp = 0; tp < 20; tp++)
-		regval = Xil_In32(0xFD070018);
-	unsigned int pll_retry = 10;
-	unsigned int pll_locked = 0;
-
-	while ((pll_retry > 0) && (!pll_locked)) {
-		Xil_Out32(0xFD080004, 0x00040010);
-		Xil_Out32(0xFD080004, 0x00040011);
-
-		while ((Xil_In32(0xFD080030) & 0x1) != 1)
-			;
-		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
-		    >> 31;
-		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
-		    >> 16;
-		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
-		pll_retry--;
-	}
-	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
-	if (!pll_locked)
-		return 0;
-
-	Xil_Out32(0xFD080004U, 0x00040063U);
-	Xil_Out32(0xFD0800C0U, 0x00000001U);
-
-	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
-		;
-	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
-
-	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
-		;
-	Xil_Out32(0xFD070010U, 0x80000018U);
-	Xil_Out32(0xFD0701B0U, 0x00000005U);
-	regval = Xil_In32(0xFD070018);
-	while ((regval & 0x1) != 0x0)
-		regval = Xil_In32(0xFD070018);
-
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	Xil_Out32(0xFD070014U, 0x00000331U);
-	Xil_Out32(0xFD070010U, 0x80000018U);
-	regval = Xil_In32(0xFD070018);
-	while ((regval & 0x1) != 0x0)
-		regval = Xil_In32(0xFD070018);
-
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	Xil_Out32(0xFD070014U, 0x00000B36U);
-	Xil_Out32(0xFD070010U, 0x80000018U);
-	regval = Xil_In32(0xFD070018);
-	while ((regval & 0x1) != 0x0)
-		regval = Xil_In32(0xFD070018);
-
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	Xil_Out32(0xFD070014U, 0x00000C56U);
-	Xil_Out32(0xFD070010U, 0x80000018U);
-	regval = Xil_In32(0xFD070018);
-	while ((regval & 0x1) != 0x0)
-		regval = Xil_In32(0xFD070018);
-
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	Xil_Out32(0xFD070014U, 0x00000E19U);
-	Xil_Out32(0xFD070010U, 0x80000018U);
-	regval = Xil_In32(0xFD070018);
-	while ((regval & 0x1) != 0x0)
-		regval = Xil_In32(0xFD070018);
-
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	regval = Xil_In32(0xFD070018);
-	Xil_Out32(0xFD070014U, 0x00001616U);
-	Xil_Out32(0xFD070010U, 0x80000018U);
-	Xil_Out32(0xFD070010U, 0x80000010U);
-	Xil_Out32(0xFD0701B0U, 0x00000005U);
-	Xil_Out32(0xFD070320U, 0x00000001U);
-	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
-		;
-	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
-	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
-	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
-	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
-	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
-	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
-	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
-	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
-	for (int tp = 0; tp < 20; tp++)
-		regval = Xil_In32(0xFD070018);
-
-	Xil_Out32(0xFD080068, cur_PLLCR0);
-	Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
-	Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
-	Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
-	Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
-	Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
-	Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
-	for (int tp = 0; tp < 20; tp++)
-		regval = Xil_In32(0xFD070018);
-
-	dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2);
-	for (int tp = 0; tp < 2000; tp++)
-		regval = Xil_In32(0xFD070018);
-
-	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
-	prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
-	prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
-	prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
-	prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
-	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
-
-	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
-		;
-	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
-
-	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
-		;
-	for (int tp = 0; tp < 2000; tp++)
-		regval = Xil_In32(0xFD070018);
-
-	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
-	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
-	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
-	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
-	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
-	for (int tp = 0; tp < 2000; tp++)
-		regval = Xil_In32(0xFD070018);
-
-	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
-	Xil_Out32(0xFD080004, 0x0014FE01);
-
-	regval = Xil_In32(0xFD080030);
-	while (regval != 0x8000007E)
-		regval = Xil_In32(0xFD080030);
-
-	Xil_Out32(0xFD080200U, 0x000091C7U);
-	regval = Xil_In32(0xFD080030);
-	while (regval != 0x80008FFF)
-		regval = Xil_In32(0xFD080030);
-
-	Xil_Out32(0xFD080200U, 0x800091C7U);
-	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
-	if (regval != 0)
-		return 0;
-	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
-	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
-	prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
-	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
-	Xil_Out32(0xFD070180U, 0x02160010U);
-	Xil_Out32(0xFD070060U, 0x00000000U);
-	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
-	for (int tp = 0; tp < 4000; tp++)
-		regval = Xil_In32(0xFD070018);
-
-	prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
-	prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
-	prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
-	prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
-	prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
-	prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
-	prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
-	prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
-	prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
-	prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
-	prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
-	prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
-	prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
-	prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
-	prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
-	prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
-
-	return 1;
-}
-
 static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate,
 			  u32 lane2_protocol, u32 lane2_rate,
 			  u32 lane1_protocol, u32 lane1_rate,
@@ -1868,6 +995,871 @@ static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly,
 	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
 }
 
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
+	psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+	serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0);
+	psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U);
+	psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+	int cur_PLLCR0;
+
+	cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL0PLLCR0;
+
+	cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL1PLLCR0;
+
+	cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL2PLLCR0;
+
+	cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL3PLLCR0;
+
+	cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL4PLLCR0;
+
+	cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SLBPLLCR0;
+
+	cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+	Xil_Out32(0xFD080068, 0x02120000);
+	Xil_Out32(0xFD081404, 0x02120000);
+	Xil_Out32(0xFD081444, 0x02120000);
+	Xil_Out32(0xFD081484, 0x02120000);
+	Xil_Out32(0xFD0814C4, 0x02120000);
+	Xil_Out32(0xFD081504, 0x02120000);
+	Xil_Out32(0xFD0817C4, 0x02120000);
+	int cur_div2;
+
+	cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U;
+	int cur_fbdiv;
+
+	cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
+	dpll_prog(1, 49, 63, 625, 3, 3, 2);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+	Xil_Out32(0xFD0800C0U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000331U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000B36U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000C56U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000E19U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00001616U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	Xil_Out32(0xFD070010U, 0x80000010U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
+	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
+	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	Xil_Out32(0xFD080068, cur_PLLCR0);
+	Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
+	Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
+	Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
+	Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
+	Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
+	Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2);
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
+	prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
+	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0014FE01);
+
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x8000007E)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x000091C7U);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80008FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
+	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
+	Xil_Out32(0xFD070180U, 0x02160010U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+	for (int tp = 0; tp < 4000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
+	prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
+	prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
+	prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
+	prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
+	prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	return 1;
+}
+
 static int serdes_enb_coarse_saturation(void)
 {
 	Xil_Out32(0xFD402094, 0x00000010);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c
index 2adcad0..f98ad8a 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c
@@ -6,766 +6,6 @@
 #include <asm/arch/psu_init_gpl.h>
 #include <xil_io.h>
 
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
-			   u32 lane2_protocol, u32 lane2_rate,
-			   u32 lane1_protocol, u32 lane1_rate,
-			   u32 lane0_protocol, u32 lane0_rate);
-
-static unsigned long psu_pll_init_data(void)
-{
-	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
-	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
-	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
-	mask_poll(0xFF5E0040, 0x00000002U);
-	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
-	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
-	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
-	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
-	mask_poll(0xFF5E0040, 0x00000001U);
-	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
-	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
-	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000001U);
-	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
-	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
-	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000002U);
-	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
-	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
-	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
-	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000004U);
-	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
-
-	return 1;
-}
-
-static unsigned long psu_clock_init_data(void)
-{
-	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
-	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
-	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
-	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
-	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
-	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
-	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
-	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
-	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
-	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
-	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
-	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
-	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
-	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
-	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
-	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
-	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
-	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
-	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
-	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_init_data(void)
-{
-	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
-	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
-	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
-	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
-	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
-	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
-	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
-	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
-	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
-	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
-	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
-	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
-	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
-	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
-	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
-	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
-	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
-	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
-	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
-	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
-	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
-	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
-	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
-	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
-	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
-	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
-	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
-	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
-	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
-	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
-	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
-	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
-	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
-	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
-	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
-	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
-	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
-	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
-	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
-	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
-	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
-	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
-	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
-	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
-	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
-	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
-	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
-	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
-	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
-	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
-	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
-	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
-	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
-	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
-	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
-	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
-	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
-	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
-	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
-	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
-	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
-	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
-	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
-	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
-	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
-	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
-	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
-	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
-	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
-	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
-	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
-	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
-	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
-	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
-	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
-	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
-	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
-	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
-	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
-	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
-	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
-	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
-	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
-	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
-	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
-	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
-	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
-	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
-	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
-	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
-	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
-	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
-	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
-	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
-	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
-	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
-	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
-	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
-	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
-	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
-	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
-	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
-	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
-	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
-	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
-	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
-	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
-	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
-	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
-	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
-	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
-	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
-	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
-	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
-	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
-	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
-	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
-	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
-	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
-	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
-	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
-	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
-	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
-	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
-	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
-	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
-	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
-	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
-	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
-	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
-	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
-	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
-	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
-	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
-	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
-	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
-	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
-	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
-	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
-	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
-	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
-	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
-	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_qos_init_data(void)
-{
-	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_mio_init_data(void)
-{
-	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
-	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
-	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
-	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
-	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
-	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_peripherals_pre_init_data(void)
-{
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
-	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
-
-	return 1;
-}
-
-static unsigned long psu_peripherals_init_data(void)
-{
-	psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
-	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
-	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
-	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
-	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
-	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
-	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
-	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
-	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
-	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
-	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
-	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
-	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
-
-	mask_delay(1);
-	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
-
-	mask_delay(5);
-	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
-
-	return 1;
-}
-
-static unsigned long psu_serdes_init_data(void)
-{
-	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
-	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
-	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
-	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
-	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
-	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
-	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
-	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
-	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
-	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
-	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
-	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
-	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
-	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
-	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
-	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
-	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
-	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
-	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
-	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
-	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
-	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
-	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
-	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
-	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
-	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
-	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
-	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
-	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
-	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
-	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
-	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
-	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
-	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
-	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
-	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
-	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
-
-	serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
-	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
-	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
-	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
-	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
-	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
-	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
-
-	return 1;
-}
-
-static unsigned long psu_resetout_init_data(void)
-{
-	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
-	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
-	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
-	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
-	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
-	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
-	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
-	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
-	mask_poll(0xFD40A3E4, 0x00000010U);
-	mask_poll(0xFD40E3E4, 0x00000010U);
-	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
-	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
-	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
-	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
-
-	return 1;
-}
-
-static unsigned long psu_resetin_init_data(void)
-{
-	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
-	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
-
-	return 1;
-}
-
-static unsigned long psu_afi_config(void)
-{
-	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
-	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
-	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
-	psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
-	psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
-	psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
-	psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_phybringup_data(void)
-{
-	unsigned int regval = 0;
-	unsigned int pll_retry = 10;
-	unsigned int pll_locked = 0;
-	int cur_R006_tREFPRD;
-
-	while ((pll_retry > 0) && (!pll_locked)) {
-		Xil_Out32(0xFD080004, 0x00040010);
-		Xil_Out32(0xFD080004, 0x00040011);
-
-		while ((Xil_In32(0xFD080030) & 0x1) != 1)
-			;
-		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
-		    >> 31;
-		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
-		    >> 16;
-		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
-		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
-		    >> 16;
-		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
-		    >> 16;
-		pll_retry--;
-	}
-	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
-	if (!pll_locked)
-		return 0;
-
-	Xil_Out32(0xFD080004U, 0x00040063U);
-
-	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
-		;
-	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
-
-	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
-		;
-	Xil_Out32(0xFD0701B0U, 0x00000001U);
-	Xil_Out32(0xFD070320U, 0x00000001U);
-	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
-		;
-	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
-	Xil_Out32(0xFD080004, 0x0004FE01);
-	regval = Xil_In32(0xFD080030);
-	while (regval != 0x80000FFF)
-		regval = Xil_In32(0xFD080030);
-	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
-	if (regval != 0)
-		return 0;
-
-	Xil_Out32(0xFD080200U, 0x100091C7U);
-
-	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
-	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
-
-	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
-	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
-	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
-	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
-	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
-	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
-
-	Xil_Out32(0xFD080004, 0x00060001);
-	regval = Xil_In32(0xFD080030);
-	while ((regval & 0x80004001) != 0x80004001)
-		regval = Xil_In32(0xFD080030);
-
-	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
-	if (regval != 0)
-		return 0;
-
-	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
-	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
-
-	Xil_Out32(0xFD080200U, 0x800091C7U);
-	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
-
-	Xil_Out32(0xFD080004, 0x0000C001);
-	regval = Xil_In32(0xFD080030);
-	while ((regval & 0x80000C01) != 0x80000C01)
-		regval = Xil_In32(0xFD080030);
-
-	Xil_Out32(0xFD070180U, 0x01000040U);
-	Xil_Out32(0xFD070060U, 0x00000000U);
-	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
-
-	return 1;
-}
-
 static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate,
 			  u32 lane2_protocol, u32 lane2_rate,
 			  u32 lane1_protocol, u32 lane1_rate,
@@ -1696,6 +936,761 @@ static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
 	return 1;
 }
 
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+	serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+	int cur_R006_tREFPRD;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
 static int serdes_enb_coarse_saturation(void)
 {
 	Xil_Out32(0xFD402094, 0x00000010);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c
index bd31687..5d47cd1 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c
@@ -6,766 +6,6 @@
 #include <asm/arch/psu_init_gpl.h>
 #include <xil_io.h>
 
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
-			   u32 lane2_protocol, u32 lane2_rate,
-			   u32 lane1_protocol, u32 lane1_rate,
-			   u32 lane0_protocol, u32 lane0_rate);
-
-static unsigned long psu_pll_init_data(void)
-{
-	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
-	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
-	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
-	mask_poll(0xFF5E0040, 0x00000002U);
-	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
-	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
-	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
-	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
-	mask_poll(0xFF5E0040, 0x00000001U);
-	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
-	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
-	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000001U);
-	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
-	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
-	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
-	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000002U);
-	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
-	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
-	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
-	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
-	mask_poll(0xFD1A0044, 0x00000004U);
-	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
-
-	return 1;
-}
-
-static unsigned long psu_clock_init_data(void)
-{
-	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
-	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
-	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
-	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
-	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
-	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
-	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
-	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
-	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
-	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
-	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
-	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
-	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
-	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
-	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
-	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
-	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
-	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
-	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
-	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
-	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_init_data(void)
-{
-	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
-	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
-	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
-	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
-	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
-	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
-	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
-	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
-	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
-	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
-	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
-	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
-	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
-	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
-	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
-	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
-	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
-	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
-	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
-	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
-	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
-	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
-	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
-	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
-	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
-	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
-	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
-	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
-	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
-	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
-	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
-	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
-	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
-	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
-	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
-	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
-	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
-	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
-	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
-	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
-	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
-	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
-	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
-	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
-	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
-	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
-	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
-	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
-	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
-	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
-	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
-	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
-	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
-	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
-	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
-	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
-	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
-	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
-	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
-	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
-	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
-	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
-	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
-	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
-	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
-	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
-	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
-	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
-	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
-	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
-	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
-	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
-	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
-	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
-	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
-	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
-	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
-	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
-	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
-	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
-	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
-	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
-	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
-	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
-	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
-	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
-	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
-	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
-	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
-	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
-	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
-	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
-	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
-	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
-	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
-	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
-	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
-	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
-	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
-	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
-	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
-	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
-	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
-	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
-	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
-	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
-	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
-	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
-	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
-	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
-	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
-	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
-	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
-	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
-	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
-	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
-	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
-	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
-	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
-	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
-	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
-	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
-	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
-	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
-	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
-	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
-	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
-	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
-	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
-	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
-	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
-	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
-	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
-	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
-	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
-	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
-	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
-	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
-	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
-	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
-	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
-	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
-	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
-	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
-	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
-	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
-	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
-	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
-	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
-	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
-	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
-	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
-	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
-	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
-	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
-	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
-	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_qos_init_data(void)
-{
-	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
-	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_mio_init_data(void)
-{
-	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
-	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
-	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
-	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
-	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
-	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
-	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
-	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
-	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
-	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
-	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
-	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
-
-	return 1;
-}
-
-static unsigned long psu_peripherals_pre_init_data(void)
-{
-	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
-	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
-
-	return 1;
-}
-
-static unsigned long psu_peripherals_init_data(void)
-{
-	psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
-	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
-	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
-	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
-	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
-	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
-	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
-	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
-	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
-	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
-	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
-	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
-	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
-
-	mask_delay(1);
-	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
-
-	mask_delay(5);
-	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
-
-	return 1;
-}
-
-static unsigned long psu_serdes_init_data(void)
-{
-	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
-	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
-	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
-	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
-	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
-	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
-	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
-	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
-	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
-	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
-	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
-	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
-	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
-	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
-	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
-	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
-	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
-	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
-	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
-	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
-	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
-	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
-	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
-	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
-	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
-	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
-	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
-	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
-	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
-	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
-	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
-	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
-	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
-	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
-	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
-	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
-	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
-	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
-	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
-	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
-	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
-	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
-	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
-	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
-
-	serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
-	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
-	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
-	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
-	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
-	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
-	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
-
-	return 1;
-}
-
-static unsigned long psu_resetout_init_data(void)
-{
-	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
-	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
-	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
-	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
-	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
-	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
-	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
-	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
-	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
-	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
-	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
-	mask_poll(0xFD40A3E4, 0x00000010U);
-	mask_poll(0xFD40E3E4, 0x00000010U);
-	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
-	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
-	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
-	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
-
-	return 1;
-}
-
-static unsigned long psu_resetin_init_data(void)
-{
-	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
-	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
-	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
-
-	return 1;
-}
-
-static unsigned long psu_afi_config(void)
-{
-	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
-	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
-	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
-	psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
-	psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
-	psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
-	psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
-
-	return 1;
-}
-
-static unsigned long psu_ddr_phybringup_data(void)
-{
-	unsigned int regval = 0;
-	unsigned int pll_retry = 10;
-	unsigned int pll_locked = 0;
-	int cur_R006_tREFPRD;
-
-	while ((pll_retry > 0) && (!pll_locked)) {
-		Xil_Out32(0xFD080004, 0x00040010);
-		Xil_Out32(0xFD080004, 0x00040011);
-
-		while ((Xil_In32(0xFD080030) & 0x1) != 1)
-			;
-		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
-		    >> 31;
-		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
-		    >> 16;
-		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
-		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
-		    >> 16;
-		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
-		    >> 16;
-		pll_retry--;
-	}
-	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
-	if (!pll_locked)
-		return 0;
-
-	Xil_Out32(0xFD080004U, 0x00040063U);
-
-	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
-		;
-	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
-
-	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
-		;
-	Xil_Out32(0xFD0701B0U, 0x00000001U);
-	Xil_Out32(0xFD070320U, 0x00000001U);
-	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
-		;
-	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
-	Xil_Out32(0xFD080004, 0x0004FE01);
-	regval = Xil_In32(0xFD080030);
-	while (regval != 0x80000FFF)
-		regval = Xil_In32(0xFD080030);
-	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
-	if (regval != 0)
-		return 0;
-
-	Xil_Out32(0xFD080200U, 0x100091C7U);
-
-	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
-	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
-
-	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
-	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
-	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
-	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
-	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
-	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
-
-	Xil_Out32(0xFD080004, 0x00060001);
-	regval = Xil_In32(0xFD080030);
-	while ((regval & 0x80004001) != 0x80004001)
-		regval = Xil_In32(0xFD080030);
-
-	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
-	if (regval != 0)
-		return 0;
-
-	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
-	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
-	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
-
-	Xil_Out32(0xFD080200U, 0x800091C7U);
-	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
-
-	Xil_Out32(0xFD080004, 0x0000C001);
-	regval = Xil_In32(0xFD080030);
-	while ((regval & 0x80000C01) != 0x80000C01)
-		regval = Xil_In32(0xFD080030);
-
-	Xil_Out32(0xFD070180U, 0x01000040U);
-	Xil_Out32(0xFD070060U, 0x00000000U);
-	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
-
-	return 1;
-}
-
 static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate,
 			  u32 lane2_protocol, u32 lane2_rate,
 			  u32 lane1_protocol, u32 lane1_rate,
@@ -1696,6 +936,761 @@ static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
 	return 1;
 }
 
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+	serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+	int cur_R006_tREFPRD;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
 static int serdes_enb_coarse_saturation(void)
 {
 	Xil_Out32(0xFD402094, 0x00000010);
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index e311aa7..106c395 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -19,6 +19,7 @@
 #include <sata.h>
 #include <ahci.h>
 #include <scsi.h>
+#include <soc.h>
 #include <malloc.h>
 #include <memalign.h>
 #include <wdt.h>
@@ -44,278 +45,10 @@
 
 #include "pm_cfg_obj.h"
 
-#define ZYNQMP_VERSION_SIZE	7
-#define EFUSE_VCU_DIS_MASK	0x100
-#define EFUSE_VCU_DIS_SHIFT	8
-#define EFUSE_GPU_DIS_MASK	0x20
-#define EFUSE_GPU_DIS_SHIFT	5
-#define IDCODE2_PL_INIT_MASK	0x200
-#define IDCODE2_PL_INIT_SHIFT	9
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
-
-enum {
-	ZYNQMP_VARIANT_EG = BIT(0U),
-	ZYNQMP_VARIANT_EV = BIT(1U),
-	ZYNQMP_VARIANT_CG = BIT(2U),
-	ZYNQMP_VARIANT_DR = BIT(3U),
-};
-
-static const struct {
-	u32 id;
-	u8 device;
-	u8 variants;
-} zynqmp_devices[] = {
-	{
-		.id = 0x04688093,
-		.device = 1,
-		.variants = ZYNQMP_VARIANT_EG,
-	},
-	{
-		.id = 0x04711093,
-		.device = 2,
-		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
-	},
-	{
-		.id = 0x04710093,
-		.device = 3,
-		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
-	},
-	{
-		.id = 0x04721093,
-		.device = 4,
-		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
-			ZYNQMP_VARIANT_EV,
-	},
-	{
-		.id = 0x04720093,
-		.device = 5,
-		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
-			ZYNQMP_VARIANT_EV,
-	},
-	{
-		.id = 0x04739093,
-		.device = 6,
-		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
-	},
-	{
-		.id = 0x04730093,
-		.device = 7,
-		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
-			ZYNQMP_VARIANT_EV,
-	},
-	{
-		.id = 0x04738093,
-		.device = 9,
-		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
-	},
-	{
-		.id = 0x04740093,
-		.device = 11,
-		.variants = ZYNQMP_VARIANT_EG,
-	},
-	{
-		.id = 0x04750093,
-		.device = 15,
-		.variants = ZYNQMP_VARIANT_EG,
-	},
-	{
-		.id = 0x04759093,
-		.device = 17,
-		.variants = ZYNQMP_VARIANT_EG,
-	},
-	{
-		.id = 0x04758093,
-		.device = 19,
-		.variants = ZYNQMP_VARIANT_EG,
-	},
-	{
-		.id = 0x047E1093,
-		.device = 21,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047E3093,
-		.device = 23,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047E5093,
-		.device = 25,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047E4093,
-		.device = 27,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047E0093,
-		.device = 28,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047E2093,
-		.device = 29,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047E6093,
-		.device = 39,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047FD093,
-		.device = 43,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047F8093,
-		.device = 46,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047FF093,
-		.device = 47,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047FB093,
-		.device = 48,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x047FE093,
-		.device = 49,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-	{
-		.id = 0x046d0093,
-		.device = 67,
-		.variants = ZYNQMP_VARIANT_DR,
-	},
-};
-
-static const struct {
-	u32 id;
-	char *name;
-} zynqmp_svd_devices[] = {
-	{
-		.id = 0x04714093,
-		.name = "xck24"
-	},
-	{
-		.id = 0x04724093,
-		.name = "xck26",
-	},
-};
-
-static char *zynqmp_detect_svd_name(u32 idcode)
-{
-	u32 i;
-
-	for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) {
-		if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF))
-			return zynqmp_svd_devices[i].name;
-	}
-
-	return "unknown";
-}
-
-static char *zynqmp_get_silicon_idcode_name(void)
-{
-	u32 i;
-	u32 idcode, idcode2;
-	char name[ZYNQMP_VERSION_SIZE];
-	u32 ret_payload[PAYLOAD_ARG_CNT];
-	int ret;
-
-	ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
-	if (ret) {
-		debug("%s: Getting chipid failed\n", __func__);
-		return "unknown";
-	}
-
-	/*
-	 * Firmware returns:
-	 * payload[0][31:0]  = status of the operation
-	 * payload[1]] = IDCODE
-	 * payload[2][19:0]  = Version
-	 * payload[2][28:20] = EXTENDED_IDCODE
-	 * payload[2][29] = PL_INIT
-	 */
-
-	idcode  = ret_payload[1];
-	idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
-	debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
-	      idcode2);
-
-	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-		if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
-			break;
-	}
-
-	if (i >= ARRAY_SIZE(zynqmp_devices))
-		return zynqmp_detect_svd_name(idcode);
-
-	/* Add device prefix to the name */
-	ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
-		       zynqmp_devices[i].device);
-	if (ret < 0)
-		return "unknown";
-
-	if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
-		/* Devices with EV variant might be EG/CG/EV family */
-		if (idcode2 & IDCODE2_PL_INIT_MASK) {
-			u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
-				      EFUSE_VCU_DIS_SHIFT) << 1 |
-				     ((idcode2 & EFUSE_GPU_DIS_MASK) >>
-				      EFUSE_GPU_DIS_SHIFT);
-
-			/*
-			 * Get family name based on extended idcode values as
-			 * determined on UG1087, EXTENDED_IDCODE register
-			 * description
-			 */
-			switch (family) {
-			case 0x00:
-				strncat(name, "ev", 2);
-				break;
-			case 0x10:
-				strncat(name, "eg", 2);
-				break;
-			case 0x11:
-				strncat(name, "cg", 2);
-				break;
-			default:
-				/* Do not append family name*/
-				break;
-			}
-		} else {
-			/*
-			 * When PL powered down the VCU Disable efuse cannot be
-			 * read. So, ignore the bit and just findout if it is CG
-			 * or EG/EV variant.
-			 */
-			strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
-				"e", 2);
-		}
-	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
-		/* Devices with CG variant might be EG or CG family */
-		strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
-	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
-		strncat(name, "eg", 2);
-	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
-		strncat(name, "dr", 2);
-	} else {
-		debug("Variant not identified\n");
-	}
-
-	return strdup(name);
-}
 #endif
 
 int __maybe_unused psu_uboot_init(void)
@@ -406,6 +139,11 @@ static void print_secure_boot(void)
 
 int board_init(void)
 {
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
+	struct udevice *soc;
+	char name[SOC_MAX_STR_SIZE];
+	int ret;
+#endif
 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 	struct udevice *dev;
 
@@ -432,10 +170,15 @@ int board_init(void)
 	printf("EL Level:\tEL%d\n", current_el());
 
 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
-	zynqmppl.name = zynqmp_get_silicon_idcode_name();
-	printf("Chip ID:\t%s\n", zynqmppl.name);
-	fpga_init();
-	fpga_add(fpga_xilinx, &zynqmppl);
+	ret = soc_get(&soc);
+	if (!ret) {
+		ret = soc_get_machine(soc, name, sizeof(name));
+		if (ret >= 0) {
+			zynqmppl.name = strdup(name);
+			fpga_init();
+			fpga_add(fpga_xilinx, &zynqmppl);
+		}
+	}
 #endif
 
 	/* display secure boot information */
@@ -924,6 +667,7 @@ void set_dfu_alt_info(char *interface, char *devstr)
 				 bootseq, multiboot, bootseq,
 				 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
 		break;
+#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
 	case QSPI_MODE_24BIT:
 	case QSPI_MODE_32BIT:
 		snprintf(buf, DFU_ALT_BUF_LEN,
@@ -932,6 +676,7 @@ void set_dfu_alt_info(char *interface, char *devstr)
 			 multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
 			 CONFIG_SYS_SPI_U_BOOT_OFFS);
 		break;
+#endif
 	default:
 		return;
 	}