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| author | Lei Wen <[leiwen@marvell.com]> | 2011-11-01 16:25:56 +0530 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-11-03 22:56:22 +0100 |
| commit | 0caac5f4155a1db6c5ce921c7f9294b6b46e7744 (patch) | |
| tree | c8749f7c0bb033051d9ea07f2d950fd527023098 /board | |
| parent | f779d739d67653c0d77f50cb18c315b2d39de075 (diff) | |
| download | u-boot-0caac5f4155a1db6c5ce921c7f9294b6b46e7744.zip u-boot-0caac5f4155a1db6c5ce921c7f9294b6b46e7744.tar.gz u-boot-0caac5f4155a1db6c5ce921c7f9294b6b46e7744.tar.bz2 | |
pantheon: define CONFIG_SYS_CACHELINE_SIZE
By default, on Pantheon SoC DCache Lnd ICache line
lengths are 32 bytes long
Signed-off-by: Lei Wen <leiwen@marvell.com>
Diffstat (limited to 'board')
0 files changed, 0 insertions, 0 deletions