Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

* Add StarFive VisionFive v2 Board support
* Support CONFIG_REMAKE_ELF
* Code cleanups for RISC-V architecture

5 files changed, 194 insertions, 0 deletions

diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig
new file mode 100644
index 0000000..2186a93
--- /dev/null
+++ b/board/starfive/visionfive2/Kconfig
@@ -0,0 +1,53 @@
+if TARGET_STARFIVE_VISIONFIVE2
+
+config SYS_CPU
+	default "jh7110"
+
+config SYS_BOARD
+	default "visionfive2"
+
+config SYS_VENDOR
+	default "starfive"
+
+config SYS_CONFIG_NAME
+	default "starfive-visionfive2"
+
+config TEXT_BASE
+	default 0x40200000 if SPL
+	default 0x40000000 if !RISCV_SMODE
+	default 0x40200000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+	default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select STARFIVE_JH7110
+	select SUPPORT_SPL
+	select BINMAN
+	imply CMD_CPU
+	imply CMD_DHCP
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_FAT
+	imply CMD_FS_GENERIC
+	imply CMD_GPIO
+	imply CMD_GPT
+	imply CMD_MMC
+	imply CMD_NET
+	imply CMD_PING
+	imply CMD_SF
+	imply DM_GPIO
+	imply DOS_PARTITION
+	imply EFI_PARTITION
+	imply MII
+	imply IP_DYN
+	imply ISO_PARTITION
+	imply PARTITION_TYPE_GUID
+	imply PHY_LIB
+	imply PHY_MSCC
+
+endif
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
new file mode 100644
index 0000000..c536908
--- /dev/null
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -0,0 +1,7 @@
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S:	Maintained
+F:	arch/riscv/include/asm/arch-jh7110/
+F:	board/starfive/visionfive2/
+F:	include/configs/starfive-visionfive2.h
+F:	configs/starfive_visionfive2_defconfig
diff --git a/board/starfive/visionfive2/Makefile b/board/starfive/visionfive2/Makefile
new file mode 100644
index 0000000..66c854d
--- /dev/null
+++ b/board/starfive/visionfive2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+#
+
+obj-y	:= starfive_visionfive2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644
index 0000000..db0b4cb
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/spl.h>
+#include <asm/io.h>
+#include <log.h>
+#include <spl.h>
+
+#define JH7110_CLK_CPU_ROOT_OFFSET		0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT		24
+#define JH7110_CLK_CPU_ROOT_MASK		GENMASK(29, 24)
+
+int spl_board_init_f(void)
+{
+	int ret;
+
+	ret = spl_soc_init();
+	if (ret) {
+		debug("JH7110 SPL init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode;
+
+	mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+				& JH7110_BOOT_MODE_SELECT_MASK;
+	switch (mode) {
+	case 0:
+		return BOOT_DEVICE_SPI;
+
+	case 1:
+		return BOOT_DEVICE_MMC2;
+
+	case 2:
+		return BOOT_DEVICE_MMC1;
+
+	case 3:
+		return BOOT_DEVICE_UART;
+
+	default:
+		debug("Unsupported boot device 0x%x.\n", mode);
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	ret = spl_early_init();
+	if (ret)
+		panic("spl_early_init() failed: %d\n", ret);
+
+	riscv_cpu_setup(NULL, NULL);
+	preloader_console_init();
+
+	/* Set the parent clock of cpu_root clock to pll0,
+	 * it must be initialized here
+	 */
+	clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
+			JH7110_CLK_CPU_ROOT_MASK,
+			BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+
+	ret = spl_board_init_f();
+	if (ret) {
+		debug("spl_board_init_f init failed: %d\n", ret);
+		return;
+	}
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
new file mode 100644
index 0000000..613fe79
--- /dev/null
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <cpu_func.h>
+#include <linux/bitops.h>
+
+#define JH7110_L2_PREFETCHER_BASE_ADDR		0x2030000
+#define JH7110_L2_PREFETCHER_HART_OFFSET	0x2000
+
+/* enable U74-mc hart1~hart4 prefetcher */
+static void enable_prefetcher(void)
+{
+	u8 hart;
+	u32 *reg;
+
+	/* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7),
+	 * but only U7 cores support prefetcher configuration
+	 */
+	for (hart = 1; hart < 5; hart++) {
+		reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR
+					+ hart * JH7110_L2_PREFETCHER_HART_OFFSET);
+
+		mb(); /* memory barrier */
+		setbits_le32(reg, 0x1);
+		mb(); /* memory barrier */
+	}
+}
+
+int board_init(void)
+{
+	enable_caches();
+	enable_prefetcher();
+
+	return 0;
+}