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| author | Chris Packham <judge.packham@gmail.com> | 2019-02-11 14:19:56 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2019-02-11 09:39:12 +0100 |
| commit | a6ac775bae7fad1534ffe2b20244b7e7106b12b0 (patch) | |
| tree | 971a69140bdef8ec899950238554fb19db0116f9 /board | |
| parent | 0ef692084363f2de8547db93397c6a69123d26ca (diff) | |
| download | u-boot-a6ac775bae7fad1534ffe2b20244b7e7106b12b0.zip u-boot-a6ac775bae7fad1534ffe2b20244b7e7106b12b0.tar.gz u-boot-a6ac775bae7fad1534ffe2b20244b7e7106b12b0.tar.bz2 | |
ARM: mvebu: x530: use MV_DDR_FREQ_SAR
MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware
strapping. This also has the side effect of running the DDR clock in
synchronous mode with the CPU core clock rather than from an independent
PLL. We've seen this improve reliability in operation across a number of
boards and temperature ranges.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/alliedtelesis/x530/x530.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index b34ae51..d7d1942 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -57,7 +57,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1866M, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ MV_DDR_DIE_CAP_4GBIT, /* die capacity */ - MV_DDR_FREQ_933, /* frequency */ + MV_DDR_FREQ_SAR, /* frequency */ 0, 0, /* cas_l cas_wl */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_2T} }, /* timing */ |