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authorTom Rini <trini@konsulko.com>2019-09-03 12:40:50 -0400
committerTom Rini <trini@konsulko.com>2019-09-03 12:40:50 -0400
commit448f11f7503995746a7b71e5e3b3a831c4651be9 (patch)
treec96746e9d64884b8ad7a2c3909f96fbfdbaad595 /board
parentf65fb411ed6576e08a22b9d236deba66ef957c31 (diff)
parent968b98bc27c2b228323c53761075422ebbb098bd (diff)
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Merge tag 'arc-for-2019.10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc
These are some very late changes mostly required to get 64-bit division working on ARC boards. For that we had to import missing parts of libgcc and add compiler flags to EMSDP which otherwise used very simple profile for compliation. And while at it another fix for EM SDP initialization is inluded as well.
Diffstat (limited to 'board')
-rw-r--r--board/synopsys/emsdp/config.mk2
-rw-r--r--board/synopsys/emsdp/emsdp.c37
2 files changed, 39 insertions, 0 deletions
diff --git a/board/synopsys/emsdp/config.mk b/board/synopsys/emsdp/config.mk
new file mode 100644
index 0000000..67fd7bf
--- /dev/null
+++ b/board/synopsys/emsdp/config.mk
@@ -0,0 +1,2 @@
+PLATFORM_CPPFLAGS += -mlittle-endian -mnorm -mswap -mmpy-option=3 \
+ -mbarrel-shifter -mfpu=fpuda_all -mcode-density
diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c
index c0770b5..7a3fd5b 100644
--- a/board/synopsys/emsdp/emsdp.c
+++ b/board/synopsys/emsdp/emsdp.c
@@ -48,6 +48,43 @@ int mach_cpu_init(void)
return 0;
}
+int board_early_init_r(void)
+{
+#define EMSDP_PSRAM_BASE 0xf2001000
+#define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10)
+#define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14)
+#define CRE_ENABLE BIT(31)
+#define CRE_DRIVE_CMD BIT(6)
+
+#define PSRAM_RCR_DPD BIT(1)
+#define PSRAM_RCR_PAGE_MODE BIT(7)
+
+/*
+ * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
+ * thus "<< 1".
+ */
+#define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
+
+ // Switch PSRAM controller to command mode
+ writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
+ // Program Refresh Configuration Register (RCR) for BANK0
+ writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
+ // Switch PSRAM controller back to memory mode
+ writel(0, PSRAM_FLASH_CONFIG_REG_0);
+
+
+ // Switch PSRAM controller to command mode
+ writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
+ // Program Refresh Configuration Register (RCR) for BANK1
+ writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
+ // Switch PSRAM controller back to memory mode
+ writel(0, PSRAM_FLASH_CONFIG_REG_1);
+
+ printf("PSRAM initialized.\n");
+
+ return 0;
+}
+
int board_mmc_init(bd_t *bis)
{
struct dwmci_host *host = NULL;