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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2018-02-28 20:51:53 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-04-03 12:11:32 +0200 |
| commit | ba1c98bae2649e990c6af04545e422042cb58b27 (patch) | |
| tree | 7fcf0b192701a86dc6314a2422f3e6542efda16c /board | |
| parent | 22f0aa0528a48cb9eb72abb065071e47c4215af9 (diff) | |
| download | u-boot-ba1c98bae2649e990c6af04545e422042cb58b27.zip u-boot-ba1c98bae2649e990c6af04545e422042cb58b27.tar.gz u-boot-ba1c98bae2649e990c6af04545e422042cb58b27.tar.bz2 | |
sunxi: spl: deassert the NAND controller reset line
Ensure the NAND controller reset line is deasserted before use.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/sunxi/board.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index e08e22f..ee3bfda 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -286,6 +286,10 @@ static void nand_clock_setup(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ + defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I + setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); +#endif #ifdef CONFIG_MACH_SUN9I setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); #else |