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| author | Yuantian Tang <andy.tang@nxp.com> | 2020-04-20 12:52:54 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-04-28 17:46:46 +0530 |
| commit | 35ad8f7af4ec7a2e449322c86c5301c48765a269 (patch) | |
| tree | 44867ef553c6001161d8cf55187bf8b0f306c256 /board | |
| parent | 33c3dfd2976e0752e69c36b27b88809c9b4ada12 (diff) | |
| download | u-boot-35ad8f7af4ec7a2e449322c86c5301c48765a269.zip u-boot-35ad8f7af4ec7a2e449322c86c5301c48765a269.tar.gz u-boot-35ad8f7af4ec7a2e449322c86c5301c48765a269.tar.bz2 | |
armv8: ls1046ardb: update the DIMM WRLVL_START value
The WRLVL_START values are optimized for old DDR MTA18ASF1G72AZ.
Update DDR struct to set new WRLVL_START values so that the new DIMM
MTA18ADF2G72AZ get optimized and the old DIMM still works.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/ls1046ardb/ddr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h index 3b4d44d..05baef23 100644 --- a/board/freescale/ls1046ardb/ddr.h +++ b/board/freescale/ls1046ardb/ddr.h @@ -32,7 +32,7 @@ static const struct board_specific_parameters udimm0[] = { {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,}, + {2, 2300, 0, 8, 7, 0x08090A0E, 0x1011120C,}, {} }; |