Merge branch 'master' of git://git.denx.de/u-boot-arm

227 files changed, 4654 insertions, 4280 deletions

diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds
index 5480d1f..8604696 100644
--- a/board/Barix/ipam390/u-boot-spl-ipam390.lds
+++ b/board/Barix/ipam390/u-boot-spl-ipam390.lds
@@ -49,5 +49,9 @@ SECTIONS
 	} >.sram
 
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
 }
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h
new file mode 100644
index 0000000..15225b0
--- /dev/null
+++ b/board/BuR/common/bur_common.h
@@ -0,0 +1,22 @@
+/*
+ * bur_comon.h
+ *
+ * common board information header for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BUR_COMMON_H_
+#define _BUR_COMMON_H_
+
+void blink(u32 blinks, u32 intervall, u32 pin);
+void pmicsetup(u32 mpupll);
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+int board_eth_init(bd_t *bis);
+
+#endif
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
new file mode 100644
index 0000000..04f3f1f
--- /dev/null
+++ b/board/BuR/common/common.c
@@ -0,0 +1,216 @@
+/*
+ * common.c
+ *
+ * common board functions for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include "bur_common.h"
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+/* --------------------------------------------------------------------------*/
+void blink(u32 blinks, u32 intervall, u32 pin)
+{
+	gpio_direction_output(pin, 0);
+	int val = 0;
+
+	do {
+		val ^= 0x01;
+		gpio_set_value(pin, val);
+		mdelay(intervall);
+	} while (blinks--);
+
+	gpio_set_value(pin, 0);
+}
+#ifdef CONFIG_SPL_BUILD
+void pmicsetup(u32 mpupll)
+{
+	int mpu_vdd;
+	int usb_cur_lim;
+
+	/* setup I2C */
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	if (i2c_probe(TPS65217_CHIP_PM)) {
+		puts("PMIC (0x24) not found! skip further initalization.\n");
+		return;
+	}
+
+	/* Get the frequency which is defined by device fuses */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
+
+	if (0 != mpupll) {
+		dpll_mpu_opp100.m = MPUPLL_M_1000;
+		printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
+	} else {
+		puts("ok.\n");
+	}
+	/*
+	 * Increase USB current limit to 1300mA or 1800mA and set
+	 * the MPU voltage controller as needed.
+	 */
+	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+	} else {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+			       usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set DCDC3 (CORE) voltage to 1.125V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set LDO3 to 1.8V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS1,
+			       TPS65217_LDO_VOLTAGE_OUT_1_8,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+	/* Set LDO4 to 3.3V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+	return;
+}
+
+/* describing port offsets of TI's CPSW block */
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+
+int board_eth_init(bd_t *bis)
+{
+	int rv = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
+
+		if (is_valid_ether_addr(mac_addr)) {
+			printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
+			       mac_addr[0], mac_addr[1], mac_addr[2],
+			       mac_addr[3], mac_addr[4], mac_addr[5]
+				);
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		}
+	}
+	writel(MII_MODE_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+	cpsw_slaves[1].phy_if =	PHY_INTERFACE_MODE_MII;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0) {
+		printf("Error %d registering CPSW switch\n", rv);
+		return 0;
+	}
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+	return rv;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW */
diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile
new file mode 100644
index 0000000..7b04b26
--- /dev/null
+++ b/board/BuR/kwb/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Petermaier <oe5hpm@oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
new file mode 100644
index 0000000..8aa16bc
--- /dev/null
+++ b/board/BuR/kwb/board.c
@@ -0,0 +1,240 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R KWB Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define KEY						(0+4)
+#define LCD_PWR						(0+5)
+#define PUSH_KEY					(0+31)
+#define USB2SD_NRST					(32+29)
+#define USB2SD_PWR					(96+13)
+/* -------------------------------------------------------------------------*/
+/* -- PSOC Resetcontroller Register defines -- */
+
+/* I2C Address of controller */
+#define	RSTCTRL_ADDR				0x75
+/* Register for CTRL-word */
+#define RSTCTRL_CTRLREG				0x01
+/* Register for giving some information to VxWorks OS */
+#define RSTCTRL_SCRATCHREG			0x04
+
+/* -- defines for RSTCTRL_CTRLREG  -- */
+#define	RSTCTRL_FORCE_PWR_NEN			0x0404
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	unsigned int oldspeed;
+	unsigned short buf;
+
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+	/*
+	 * enable additional clocks of modules which are accessed later from
+	 * VxWorks OS
+	 */
+	u32 *const clk_domains[] = { 0 };
+
+	u32 *const clk_modules_kwbspecific[] = {
+		&cmwkup->wkup_adctscctrl,
+		&cmper->spi1clkctrl,
+		&cmper->dcan0clkctrl,
+		&cmper->dcan1clkctrl,
+		&cmper->epwmss0clkctrl,
+		&cmper->epwmss1clkctrl,
+		&cmper->epwmss2clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
+
+	/* power-OFF LCD-Display */
+	gpio_direction_output(LCD_PWR, 0);
+
+	/* setup I2C */
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	/* power-ON  3V3 via Resetcontroller */
+	oldspeed = i2c_get_bus_speed();
+	if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+		buf = RSTCTRL_FORCE_PWR_NEN;
+		i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
+			  (uint8_t *)&buf, sizeof(buf));
+		i2c_set_bus_speed(oldspeed);
+	} else {
+		puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
+	}
+
+#if defined(CONFIG_AM335X_USB0)
+	/* power on USB2SD Controller */
+	gpio_direction_output(USB2SD_PWR, 1);
+	mdelay(1);
+	/* give a reset Pulse to USB2SD Controller */
+	gpio_direction_output(USB2SD_NRST, 0);
+	mdelay(1);
+	gpio_set_value(USB2SD_NRST, 1);
+#endif
+	pmicsetup(0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gpmc_init();
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	const unsigned int ton  = 250;
+	const unsigned int toff = 1000;
+	unsigned int cnt  = 3;
+	unsigned short buf = 0xAAAA;
+	unsigned int oldspeed;
+
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			   TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+
+	if (gpio_get_value(KEY)) {
+		do {
+			/* turn on light */
+			tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+					   TPS65217_WLEDCTRL1, 0x09, 0xFF);
+			mdelay(ton);
+			/* turn off light */
+			tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+					   TPS65217_WLEDCTRL1, 0x01, 0xFF);
+			mdelay(toff);
+			cnt--;
+			if (!gpio_get_value(KEY) &&
+			    gpio_get_value(PUSH_KEY) && 1 == cnt) {
+				puts("updating from USB ...\n");
+				setenv("bootcmd", "run usbupdate");
+				break;
+			} else if (!gpio_get_value(KEY)) {
+				break;
+			}
+		} while (cnt);
+	}
+
+	switch (cnt) {
+	case 0:
+		puts("3 blinks ... entering BOOT mode.\n");
+		buf = 0x0000;
+		break;
+	case 1:
+		puts("2 blinks ... entering DIAGNOSE mode.\n");
+		buf = 0x0F0F;
+		break;
+	case 2:
+		puts("1 blinks ... entering SERVICE mode.\n");
+		buf = 0xB4B4;
+		break;
+	case 3:
+		puts("0 blinks ... entering RUN mode.\n");
+		buf = 0x0404;
+		break;
+	}
+	mdelay(ton);
+	/* turn on light */
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			   TPS65217_WLEDCTRL1, 0x09, 0xFF);
+	/* write bootinfo into scratchregister of resetcontroller */
+	oldspeed = i2c_get_bus_speed();
+	if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+		i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+			  (uint8_t *)&buf, sizeof(buf));
+		i2c_set_bus_speed(oldspeed);
+	} else {
+		puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+	}
+	/*
+	 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+	 * expect that vectors are there, original u-boot moves them to _start
+	 */
+	__asm__("ldr r0,=0x20000");
+	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
new file mode 100644
index 0000000..1a5ffd5
--- /dev/null
+++ b/board/BuR/kwb/mux.c
@@ -0,0 +1,195 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux usb0_pin_mux[] = {
+	{OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
+	/* USB0 DrvBus Receiver disable (from romcode 0x20) */
+	{OFFSET(usb0_drvvbus), (MODE(0))},
+	/* USB1 DrvBus as GPIO due to HW-Workaround */
+	{OFFSET(usb1_drvvbus), (MODE(7))},
+	{-1},
+};
+static struct module_pin_mux spi1_pin_mux[] = {
+	/* SPI1_SCLK */
+	{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN |             RXACTIVE},
+	/* SPI1_D0 */
+	{OFFSET(mcasp0_fsx),   MODE(3) | PULLUDEN |		RXACTIVE},
+	/* SPI1_D1 */
+	{OFFSET(mcasp0_axr0),  MODE(3) | PULLUDEN |             RXACTIVE},
+	/* SPI1_CS0 */
+	{OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+	/* DCAN0 TX */
+	{OFFSET(uart1_ctsn),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN0 RX */
+	{OFFSET(uart1_rtsn),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+	/* DCAN1 TX */
+	{OFFSET(uart1_rxd),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN1 RX */
+	{OFFSET(uart1_txd),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux gpios[] = {
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+	/* GPIO0_4  (SPI D1) - TA602 */
+	{OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_5  (SPI CS0) - DISPLAY_ON_OFF */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
+	/* GPIO0_7  (PWW0 OUT) - CAN TERM */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
+	{OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+	/* GPIO0_30 (GPMC_WAIT0) - TA601 */
+	{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+	/* GPIO2_0  (GPMC_nCS3)	- VBAT_OK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO2_2  (GPMC_nADV_ALE) - DCOK */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO2_4  (GPMC_nWE) - TST_BAST */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+	/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+	{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+	{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+	{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(usb0_pin_mux);
+	configure_module_pin_mux(spi1_pin_mux);
+	configure_module_pin_mux(dcan0_pin_mux);
+	configure_module_pin_mux(dcan1_pin_mux);
+	configure_module_pin_mux(mmc1_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpios);
+}
diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile
new file mode 100644
index 0000000..ec0d27a
--- /dev/null
+++ b/board/BuR/tseries/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y	:= mux.o
+endif
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c
new file mode 100644
index 0000000..f0510e5
--- /dev/null
+++ b/board/BuR/tseries/board.c
@@ -0,0 +1,147 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R LEIT Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+/* -- defines for GPIO -- */
+#define	ETHLED_ORANGE	(96+16)	/* GPIO3_16 */
+#define	REPSWITCH	(0+20)	/* GPIO0_20 */
+
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * called from spl_nand.c
+ * return 0 for loading linux, return 1 for loading u-boot
+ */
+int spl_start_uboot(void)
+{
+	if (0 == gpio_get_value(REPSWITCH)) {
+		blink(5, 125, ETHLED_ORANGE);
+		mdelay(1000);
+		printf("SPL: entering u-boot instead kernel image.\n");
+		return 1;
+	}
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#define OSC	(V_OSCK/1000000)
+static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	pmicsetup(1000);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* Basic board specific setup.  Pinmux has been handled already. */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	gpio_direction_output(ETHLED_ORANGE, 0);
+
+	if (0 == gpio_get_value(REPSWITCH)) {
+		printf("\n\n\n"
+		"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
+		"!!!!!!! recovery switch activated !!!!!!!\n"
+		"!!!!!!!     running usbupdate     !!!!!!!\n"
+		"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
+		setenv("bootcmd", "sleep 2; run netupdate;");
+	}
+
+	printf("turning on display power+backlight ... ");
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
+			   0x09, TPS65217_MASK_ALL_BITS);	/* 200 Hz, ON */
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
+			   0x62, TPS65217_MASK_ALL_BITS);	/* 100% */
+	printf("ok.\n");
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
new file mode 100644
index 0000000..3c76e96
--- /dev/null
+++ b/board/BuR/tseries/mux.c
@@ -0,0 +1,225 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+	{-1},
+};
+#endif
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI0_SCLK */
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_D0 */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |	PULLUDEN | PULLUP_EN)},
+	/* SPI0_D1 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_CS0 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mii2_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(1)},		/* MII2_TXEN */
+	{OFFSET(gpmc_a1), MODE(1) | RXACTIVE},	/* MII2_RXDV */
+	{OFFSET(gpmc_a2), MODE(1)},		/* MII2_TXD3 */
+	{OFFSET(gpmc_a3), MODE(1)},		/* MII2_TXD2 */
+	{OFFSET(gpmc_a4), MODE(1)},		/* MII2_TXD1 */
+	{OFFSET(gpmc_a5), MODE(1)},		/* MII2_TXD0 */
+	{OFFSET(gpmc_a6), MODE(1) | RXACTIVE},	/* MII2_TXCLK */
+	{OFFSET(gpmc_a7), MODE(1) | RXACTIVE},	/* MII2_RXCLK */
+	{OFFSET(gpmc_a8), MODE(1) | RXACTIVE},	/* MII2_RXD3 */
+	{OFFSET(gpmc_a9), MODE(1) | RXACTIVE},	/* MII2_RXD2 */
+	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	/* MII2_RXD1 */
+	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	/* MII2_RXD0 */
+	{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+						/*
+						 * MII2_CRS is shared with
+						 * NAND_WAIT0
+						 */
+	{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
+	{-1},
+};
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+static struct module_pin_mux gpIOs[] = {
+	/* GPIO0_6  (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
+	{OFFSET(spi0_cs1),  (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* TIMER5   (MMC0_DAT3) - TIMER5 (Buzzer) */
+	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
+	/* TIMER6   (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
+	{OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_28 (MMC0_DAT1)	 - MII_nNAND */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_29 (MMC0_DAT0)	 - NAND_1n0 */
+	{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
+	{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN  | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
+	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
+	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_0  (GPMC_nCS3) - DCOK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/*
+	 * GPIO0_7 (PWW0 OUT)
+	 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
+	 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */
+	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - REP-Switch */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
+	{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
+	{OFFSET(mcasp0_fsx),   (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
+	{OFFSET(mcasp0_axr0),  (MODE(7) | PULLUDDIS) },
+	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
+
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mii2_pin_mux);
+#ifdef CONFIG_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_MMC)
+	configure_module_pin_mux(mmc1_pin_mux);
+#endif
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpIOs);
+}
diff --git a/board/actux1/Makefile b/board/actux1/Makefile
deleted file mode 100644
index 05a8669..0000000
--- a/board/actux1/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= actux1.o
diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c
deleted file mode 100644
index 03ccd93..0000000
--- a/board/actux1/actux1.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "actux1_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* CS5: Debug port */
-	writel(0x9d520003, IXP425_EXP_CS5);
-	/* CS6: HwRel */
-	writel(0x81860001, IXP425_EXP_CS6);
-	/* CS7: LEDs */
-	writel(0x80900003, IXP425_EXP_CS7);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-
-	/* Setup GPIOs for PCI INTA */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
-
-	/* Setup GPIOs for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
-	udelay(533);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-
-	ACTUX1_LED1(2);
-	ACTUX1_LED2(2);
-	ACTUX1_LED3(0);
-	ACTUX1_LED4(0);
-	ACTUX1_LED5(0);
-	ACTUX1_LED6(0);
-	ACTUX1_LED7(0);
-
-	ACTUX1_HS(ACTUX1_HS_DCD);
-
-	return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: AcTux-1 rev.");
-	putc(ACTUX1_BOARDREL + 'A' - 1);
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	return ACTUX1_BOARDREL;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_ixp_init(&hose);
-}
-#endif
-
-void reset_phy(void)
-{
-	u16 id1, id2;
-
-	/* initialize the PHY */
-	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
-
-	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
-	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
-
-	id2 &= 0xFFF0;		/* mask out revision bits */
-
-	if (id1 == 0x13 && id2 == 0x78e0) {
-		/*
-		 * LXT971/LXT972 PHY: set LED outputs:
-		 * LED1(green) = Link/ACT,
-		 * LED2 (unused) = LINK,
-		 * LED3(red) = Coll
-		 */
-		miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
-	} else if (id1 == 0x143 && id2 == 0xbc30) {
-		/* BCM5241: default values are OK */
-	} else
-		printf("unknown ethernet PHY ID: %x %x\n", id1, id2);
-}
diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h
deleted file mode 100644
index 5627f24..0000000
--- a/board/actux1/actux1_hw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-1 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ACTUX1_HW_H
-#define _ACTUX1_HW_H
-
-/* 0 = LED off,1 = green, 2 = red, 3 = orange */
-#define ACTUX1_LED1(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX1_LED2(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX1_LED3(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX1_LED4(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-#define ACTUX1_LED5(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
-#define ACTUX1_LED6(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
-#define ACTUX1_LED7(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
-#define ACTUX1_HS(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
-#define ACTUX1_HS_DCD	0x01
-#define ACTUX1_HS_DSR	0x02
-
-#define ACTUX1_DBG_PORT	IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX1_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-
-/* GPIO settings */
-#define CONFIG_SYS_GPIO_PCI1_INTA		2
-#define CONFIG_SYS_GPIO_PCI2_INTA		3
-#define CONFIG_SYS_GPIO_I2C_SDA		4
-#define CONFIG_SYS_GPIO_I2C_SCL		5
-#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CONFIG_SYS_GPIO_DTR			12
-#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
-
-#endif
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
deleted file mode 100644
index 4716e4f..0000000
--- a/board/actux1/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN (4);
-	.text : {
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		net/built-in.o(.text*)
-		board/actux1/built-in.o(.text*)
-		arch/arm/cpu/ixp/built-in.o(.text*)
-		drivers/input/built-in.o(.text*)
-
-		. = env_offset;
-		common/env_embedded.o(.ppcenv)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-	. = ALIGN(4);
-	.got : {
-		*(.got)
-	}
-	. =.;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN (4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	.dynsym _end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/actux2/Makefile b/board/actux2/Makefile
deleted file mode 100644
index 24cbff1..0000000
--- a/board/actux2/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= actux2.o
diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c
deleted file mode 100644
index e578cd0..0000000
--- a/board/actux2/actux2.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-
-#include <miiphy.h>
-
-#include "actux2_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* CS1: IPAC-X */
-	writel(0x94d10013, IXP425_EXP_CS1);
-	/* CS5: Debug port */
-	writel(0x9d520003, IXP425_EXP_CS5);
-	/* CS6: HW release register */
-	writel(0x81860001, IXP425_EXP_CS6);
-	/* CS7: LEDs */
-	writel(0x80900003, IXP425_EXP_CS7);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
-
-	/* Setup GPIOs for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
-
-	/* Setup GPIOs for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
-	udelay(533);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
-
-	ACTUX2_LED1(1);
-	ACTUX2_LED2(0);
-	ACTUX2_LED3(0);
-	ACTUX2_LED4(0);
-
-	return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: AcTux-2 rev.");
-	putc(ACTUX2_BOARDREL + 'A' - 1);
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	return ACTUX2_BOARDREL;
-}
-
-void reset_phy(void)
-{
-	/* init IcPlus IP175C ethernet switch to native IP175C mode */
-	miiphy_write("NPE0", 29, 31, 0x175C);
-}
diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h
deleted file mode 100644
index 57c6fa7..0000000
--- a/board/actux2/actux2_hw.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-2 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ACTUX2_HW_H
-#define _ACTUX2_HW_H
-
-/* 0 = LED off,1 = green, 2 = red, 3 = orange */
-#define ACTUX2_LED1(a)	writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX2_LED2(a)	writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX2_LED3(a)	writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX2_LED4(a)	writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-
-#define ACTUX2_DBG_PORT	IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX2_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-#define ACTUX2_OPTION	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_DBGINT			0
-#define CONFIG_SYS_GPIO_ETHINT			1
-#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
-#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
-#define CONFIG_SYS_GPIO_UNUSED4		4
-#define CONFIG_SYS_GPIO_UNUSED5		5
-#define CONFIG_SYS_GPIO_DSR			6	/* Out */
-#define CONFIG_SYS_GPIO_DCD			7	/* Out */
-#define CONFIG_SYS_GPIO_IPAC_INT		8
-#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CONFIG_SYS_GPIO_DTR			12
-#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
-
-#endif
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
deleted file mode 100644
index f00d7c7..0000000
--- a/board/actux2/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN (4);
-	.text : {
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		net/built-in.o(.text*)
-		board/actux2/built-in.o(.text*)
-		arch/arm/cpu/ixp/built-in.o(.text*)
-		drivers/input/built-in.o(.text*)
-
-		. = env_offset;
-		common/env_embedded.o(.ppcenv)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-	. = ALIGN(4);
-	.got : {
-		*(.got)
-	}
-	. =.;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN (4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	.dynsym _end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/actux3/Makefile b/board/actux3/Makefile
deleted file mode 100644
index f628f26..0000000
--- a/board/actux3/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= actux3.o
diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c
deleted file mode 100644
index 09c803c..0000000
--- a/board/actux3/actux3.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include "actux3_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* CS1: IPAC-X */
-	writel(0x94d10013, IXP425_EXP_CS1);
-	/* CS5: Debug port */
-	writel(0x9d520003, IXP425_EXP_CS5);
-	/* CS6: Release/Option register */
-	writel(0x81860001, IXP425_EXP_CS6);
-	/* CS7: LEDs */
-	writel(0x80900003, IXP425_EXP_CS7);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
-
-	/*
-	 * Setup GPIO's for Interrupt inputs
-	 */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
-
-	/*
-	 * Setup GPIO's for 33MHz clock output
-	 */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
-	/* we need a minimum PCI reset pulse width after enabling the clock */
-	udelay(533);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
-
-	ACTUX3_LED1_RT(1);
-	ACTUX3_LED1_GN(0);
-	ACTUX3_LED2_RT(0);
-	ACTUX3_LED2_GN(0);
-	ACTUX3_LED3_RT(0);
-	ACTUX3_LED3_GN(0);
-	ACTUX3_LED4_GN(0);
-	ACTUX3_LED5_RT(0);
-
-	return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: AcTux-3 rev.");
-	putc(ACTUX3_BOARDREL + 'A' - 1);
-
-	if (i > 0) {
-		puts (", serial# ");
-		puts (buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	return ACTUX3_BOARDREL;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-void reset_phy(void)
-{
-	int i;
-
-	/* initialize the PHY */
-	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
-
-	/* all LED outputs = Link/Act */
-	miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
-
-	/*
-	 * The Marvell 88E6060 switch comes up with all ports disabled.
-	 * set all ethernet switch ports to forwarding state
-	*/
-	for (i = 1; i <= 5; i++)
-		miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
-
-}
diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h
deleted file mode 100644
index f8acb4d..0000000
--- a/board/actux3/actux3_hw.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-3 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ACTUX3_HW_H
-#define _ACTUX3_HW_H
-
-/* 0 = LED off,1 = ON */
-#define ACTUX3_LED1_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX3_LED1_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX3_LED2_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX3_LED2_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-#define ACTUX3_LED3_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
-#define ACTUX3_LED3_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
-#define ACTUX3_LED4_GN(a)	writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
-#define ACTUX3_LED5_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
-
-#define ACTUX3_DBG_PORT		IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX3_BOARDREL		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-#define ACTUX3_OPTION		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
-
-/* GPIO settings */
-#define CONFIG_SYS_GPIO_DBGINT			0
-#define CONFIG_SYS_GPIO_ETHINT			1
-#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
-#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
-#define CONFIG_SYS_GPIO_LED6_RT		4	/* Out */
-#define CONFIG_SYS_GPIO_LED6_GN		5	/* Out */
-#define CONFIG_SYS_GPIO_DSR			6	/* Out */
-#define CONFIG_SYS_GPIO_DCD			7	/* Out */
-#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CONFIG_SYS_GPIO_DTR			12
-#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
-
-#endif
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
deleted file mode 100644
index 2de3ca6..0000000
--- a/board/actux3/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN (4);
-	.text : {
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		net/built-in.o(.text*)
-		board/actux3/built-in.o(.text*)
-		arch/arm/cpu/ixp/built-in.o(.text*)
-		drivers/input/built-in.o(.text*)
-
-		. = env_offset;
-		common/env_embedded.o(.ppcenv)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-	. = ALIGN(4);
-	.got : {
-		*(.got)
-	}
-	. =.;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN (4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		__bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	.dynsym _end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/actux4/Makefile b/board/actux4/Makefile
deleted file mode 100644
index b949b60..0000000
--- a/board/actux4/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= actux4.o
diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c
deleted file mode 100644
index 81c5458..0000000
--- a/board/actux4/actux4.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "actux4_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	writel(0xbd113c42, IXP425_EXP_CS1);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-
-	/* led not populated on board*/
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
-
-	/* middle LED */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
-
-	/* right LED */
-	/* weak pulldown = LED weak on */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
-
-	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
-
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
-
-	/* Setup GPIO's for 33MHz clock output */
-	writel(0x011001FF, IXP425_GPIO_GPCLKR);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-
-	udelay(10000);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-	udelay(10000);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	udelay(10000);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-
-	return 0;
-}
-
-/* Check Board Identity */
-int checkboard(void)
-{
-	puts("Board: AcTux-4\n");
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_ixp_init(&hose);
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
- * Flash 1 is an Intel *16 flash using the CFI driver.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	if (banknum == 0) {	/* non-CFI boot flash */
-		info->portwidth = 1;
-		info->chipwidth = 1;
-		info->interface = FLASH_CFI_X8;
-		return 1;
-	} else
-		return 0;
-}
diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h
deleted file mode 100644
index b936376..0000000
--- a/board/actux4/actux4_hw.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-4 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ACTUX4_HW_H
-#define _ACTUX4_HW_H
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_USBINTA		0
-#define CONFIG_SYS_GPIO_USBINTB		1
-#define CONFIG_SYS_GPIO_USBINTC		2
-#define CONFIG_SYS_GPIO_nPWRON			3	/* Out */
-#define CONFIG_SYS_GPIO_I2C_SCL		4
-#define CONFIG_SYS_GPIO_I2C_SDA		5
-#define CONFIG_SYS_GPIO_PCI_INTB		6
-#define CONFIG_SYS_GPIO_BUTTON1		7
-#define CONFIG_SYS_GPIO_LED1			8	/* Out */
-#define CONFIG_SYS_GPIO_RTCINT			9
-#define CONFIG_SYS_GPIO_LED2			10	/* Out */
-#define CONFIG_SYS_GPIO_PCI_INTA		11
-#define CONFIG_SYS_GPIO_IORST			12	/* Out */
-#define CONFIG_SYS_GPIO_LED3			13	/* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
-
-#endif
diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk
index d7e7894..c7cfaca 100644
--- a/board/ait/cam_enc_4xx/config.mk
+++ b/board/ait/cam_enc_4xx/config.mk
@@ -9,7 +9,7 @@
 
 UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
 ifndef CONFIG_SPL_BUILD
-ALL-y += $(obj)u-boot.ubl
+ALL-y += u-boot.ubl
 else
 # as SPL_TEXT_BASE is not page-aligned, we need for some
 # linkers the -n flag (Do not page align data), to prevent
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
index fdfbfc3..c0d09ad 100644
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -48,5 +48,9 @@ SECTIONS
 	} >.sram
 
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
 }
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
index aa126d7..5ab9471 100644
--- a/board/altera/nios2-generic/nios2-generic.c
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -16,7 +16,8 @@
 
 void text_base_hook(void); /* nop hook for text_base.S */
 
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
+    defined(CONFIG_CFI_FLASH_MTD)
 static void __early_flash_cmd_reset(void)
 {
 	/* reset flash before we read env */
@@ -37,7 +38,8 @@ int board_early_init_f(void)
 			"led");
 #endif
 #endif
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
+    defined(CONFIG_CFI_FLASH_MTD)
 	early_flash_cmd_reset();
 #endif
 	return 0;
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 576066b..a960eb6 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -12,6 +12,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_DISPLAY_CPUINFO)
 /*
  * Print CPU information
  */
@@ -20,6 +21,7 @@ int print_cpuinfo(void)
 	puts("CPU   : Altera SOCFPGA Platform\n");
 	return 0;
 }
+#endif
 
 /*
  * Print Board information
diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S
index 389d5e9..0fb42ad 100644
--- a/board/armltd/integrator/lowlevel_init.S
+++ b/board/armltd/integrator/lowlevel_init.S
@@ -183,7 +183,7 @@ cm_remap:
 
 	/* Now 0x00000000 is writeable, replace the vectors	*/
 	ldr	r0, =_start	/* r0 <- start of vectors	*/
-	ldr	r2, =_TEXT_BASE	/* r2 <- past vectors	*/
+	add	r2, r0, #64	/* r2 <- past vectors	*/
 	sub	r1,r1,r1		/* destination 0x00000000	*/
 
 copy_vec:
diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts
deleted file mode 100644
index a9a07f9..0000000
--- a/board/avionic-design/dts/tegra20-medcom-wide.dts
+++ /dev/null
@@ -1,77 +0,0 @@
-/dts-v1/;
-
-#include "tegra20-tamonten.dtsi"
-
-/ {
-	model = "Avionic Design Medcom-Wide";
-	compatible = "ad,medcom-wide", "nvidia,tegra20";
-
-	aliases {
-		usb0 = "/usb@c5008000";
-		sdhci0 = "/sdhci@c8000600";
-	};
-
-	memory {
-		reg = <0x00000000 0x20000000>;
-	};
-
-	host1x {
-		status = "okay";
-
-		dc@54200000 {
-			status = "okay";
-
-			rgb {
-				nvidia,panel = <&lcd_panel>;
-				status = "okay";
-			};
-		};
-	};
-
-	serial@70006300 {
-		clock-frequency = <216000000>;
-	};
-
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		status = "disabled";
-	};
-
-	usb@c5000000 {
-		status = "disabled";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
-	};
-
-	lcd_panel: panel {
-		clock = <61715000>;
-		xres = <1366>;
-		yres = <768>;
-		left-margin = <2>;
-		right-margin = <47>;
-		hsync-len = <136>;
-		lower-margin = <21>;
-		upper-margin = <11>;
-		vsync-len = <4>;
-
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 0 500000>;
-		nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
-		nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
-		nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
-		nvidia,panel-timings = <0 0 0 0>;
-	};
-};
diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts
deleted file mode 100644
index 20016f2..0000000
--- a/board/avionic-design/dts/tegra20-plutux.dts
+++ /dev/null
@@ -1,45 +0,0 @@
-/dts-v1/;
-
-#include "tegra20-tamonten.dtsi"
-
-/ {
-	model = "Avionic Design Plutux";
-	compatible = "ad,plutux", "nvidia,tegra20";
-
-	aliases {
-		usb0 = "/usb@c5008000";
-		sdhci0 = "/sdhci@c8000600";
-	};
-
-	memory {
-		reg = <0x00000000 0x20000000>;
-	};
-
-	serial@70006300 {
-		clock-frequency = <216000000>;
-	};
-
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		status = "disabled";
-	};
-
-	usb@c5000000 {
-		status = "disabled";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
-	};
-};
diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/board/avionic-design/dts/tegra20-tamonten.dtsi
deleted file mode 100644
index f379622..0000000
--- a/board/avionic-design/dts/tegra20-tamonten.dtsi
+++ /dev/null
@@ -1,500 +0,0 @@
-#include "tegra20.dtsi"
-
-/ {
-	model = "Avionic Design Tamonten SOM";
-	compatible = "ad,tamonten", "nvidia,tegra20";
-
-	memory {
-		reg = <0x00000000 0x20000000>;
-	};
-
-	host1x {
-		hdmi {
-			vdd-supply = <&hdmi_vdd_reg>;
-			pll-supply = <&hdmi_pll_reg>;
-
-			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
-		};
-	};
-
-	pinmux {
-		pinctrl-names = "default";
-		pinctrl-0 = <&state_default>;
-
-		state_default: pinmux {
-			ata {
-				nvidia,pins = "ata";
-				nvidia,function = "ide";
-			};
-			atb {
-				nvidia,pins = "atb", "gma", "gme";
-				nvidia,function = "sdio4";
-			};
-			atc {
-				nvidia,pins = "atc";
-				nvidia,function = "nand";
-			};
-			atd {
-				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
-					"spia", "spib", "spic";
-				nvidia,function = "gmi";
-			};
-			cdev1 {
-				nvidia,pins = "cdev1";
-				nvidia,function = "plla_out";
-			};
-			cdev2 {
-				nvidia,pins = "cdev2";
-				nvidia,function = "pllp_out4";
-			};
-			crtp {
-				nvidia,pins = "crtp";
-				nvidia,function = "crt";
-			};
-			csus {
-				nvidia,pins = "csus";
-				nvidia,function = "vi_sensor_clk";
-			};
-			dap1 {
-				nvidia,pins = "dap1";
-				nvidia,function = "dap1";
-			};
-			dap2 {
-				nvidia,pins = "dap2";
-				nvidia,function = "dap2";
-			};
-			dap3 {
-				nvidia,pins = "dap3";
-				nvidia,function = "dap3";
-			};
-			dap4 {
-				nvidia,pins = "dap4";
-				nvidia,function = "dap4";
-			};
-			dta {
-				nvidia,pins = "dta", "dtd";
-				nvidia,function = "sdio2";
-			};
-			dtb {
-				nvidia,pins = "dtb", "dtc", "dte";
-				nvidia,function = "rsvd1";
-			};
-			dtf {
-				nvidia,pins = "dtf";
-				nvidia,function = "i2c3";
-			};
-			gmc {
-				nvidia,pins = "gmc";
-				nvidia,function = "uartd";
-			};
-			gpu7 {
-				nvidia,pins = "gpu7";
-				nvidia,function = "rtck";
-			};
-			gpv {
-				nvidia,pins = "gpv", "slxa", "slxk";
-				nvidia,function = "pcie";
-			};
-			hdint {
-				nvidia,pins = "hdint";
-				nvidia,function = "hdmi";
-			};
-			i2cp {
-				nvidia,pins = "i2cp";
-				nvidia,function = "i2cp";
-			};
-			irrx {
-				nvidia,pins = "irrx", "irtx";
-				nvidia,function = "uarta";
-			};
-			kbca {
-				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
-					"kbce", "kbcf";
-				nvidia,function = "kbc";
-			};
-			lcsn {
-				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
-					"ld3", "ld4", "ld5", "ld6", "ld7",
-					"ld8", "ld9", "ld10", "ld11", "ld12",
-					"ld13", "ld14", "ld15", "ld16", "ld17",
-					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
-					"lhs", "lm0", "lm1", "lpp", "lpw0",
-					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
-					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
-					"lvs";
-				nvidia,function = "displaya";
-			};
-			owc {
-				nvidia,pins = "owc", "spdi", "spdo", "uac";
-				nvidia,function = "rsvd2";
-			};
-			pmc {
-				nvidia,pins = "pmc";
-				nvidia,function = "pwr_on";
-			};
-			rm {
-				nvidia,pins = "rm";
-				nvidia,function = "i2c1";
-			};
-			sdb {
-				nvidia,pins = "sdb", "sdc", "sdd";
-				nvidia,function = "pwm";
-			};
-			sdio1 {
-				nvidia,pins = "sdio1";
-				nvidia,function = "sdio1";
-			};
-			slxc {
-				nvidia,pins = "slxc", "slxd";
-				nvidia,function = "spdif";
-			};
-			spid {
-				nvidia,pins = "spid", "spie", "spif";
-				nvidia,function = "spi1";
-			};
-			spig {
-				nvidia,pins = "spig", "spih";
-				nvidia,function = "spi2_alt";
-			};
-			uaa {
-				nvidia,pins = "uaa", "uab", "uda";
-				nvidia,function = "ulpi";
-			};
-			uad {
-				nvidia,pins = "uad";
-				nvidia,function = "irda";
-			};
-			uca {
-				nvidia,pins = "uca", "ucb";
-				nvidia,function = "uartc";
-			};
-			conf_ata {
-				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
-					"cdev1", "cdev2", "dap1", "dtb", "gma",
-					"gmb", "gmc", "gmd", "gme", "gpu7",
-					"gpv", "i2cp", "pta", "rm", "slxa",
-					"slxk", "spia", "spib", "uac";
-				nvidia,pull = <0>;
-				nvidia,tristate = <0>;
-			};
-			conf_ck32 {
-				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
-					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-				nvidia,pull = <0>;
-			};
-			conf_csus {
-				nvidia,pins = "csus", "spid", "spif";
-				nvidia,pull = <1>;
-				nvidia,tristate = <1>;
-			};
-			conf_crtp {
-				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
-					"dtc", "dte", "dtf", "gpu", "sdio1",
-					"slxc", "slxd", "spdi", "spdo", "spig",
-					"uda";
-				nvidia,pull = <0>;
-				nvidia,tristate = <1>;
-			};
-			conf_ddc {
-				nvidia,pins = "ddc", "dta", "dtd", "kbca",
-					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
-					"sdc";
-				nvidia,pull = <2>;
-				nvidia,tristate = <0>;
-			};
-			conf_hdint {
-				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
-					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
-					"lvp0", "owc", "sdb";
-				nvidia,tristate = <1>;
-			};
-			conf_irrx {
-				nvidia,pins = "irrx", "irtx", "sdd", "spic",
-					"spie", "spih", "uaa", "uab", "uad",
-					"uca", "ucb";
-				nvidia,pull = <2>;
-				nvidia,tristate = <1>;
-			};
-			conf_lc {
-				nvidia,pins = "lc", "ls";
-				nvidia,pull = <2>;
-			};
-			conf_ld0 {
-				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
-					"ld5", "ld6", "ld7", "ld8", "ld9",
-					"ld10", "ld11", "ld12", "ld13", "ld14",
-					"ld15", "ld16", "ld17", "ldi", "lhp0",
-					"lhp1", "lhp2", "lhs", "lm0", "lpp",
-					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
-					"lvs", "pmc";
-				nvidia,tristate = <0>;
-			};
-			conf_ld17_0 {
-				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
-					"ld23_22";
-				nvidia,pull = <1>;
-			};
-		};
-
-		state_i2cmux_ddc: pinmux_i2cmux_ddc {
-			ddc {
-				nvidia,pins = "ddc";
-				nvidia,function = "i2c2";
-			};
-			pta {
-				nvidia,pins = "pta";
-				nvidia,function = "rsvd4";
-			};
-		};
-
-		state_i2cmux_pta: pinmux_i2cmux_pta {
-			ddc {
-				nvidia,pins = "ddc";
-				nvidia,function = "rsvd4";
-			};
-			pta {
-				nvidia,pins = "pta";
-				nvidia,function = "i2c2";
-			};
-		};
-
-		state_i2cmux_idle: pinmux_i2cmux_idle {
-			ddc {
-				nvidia,pins = "ddc";
-				nvidia,function = "rsvd4";
-			};
-			pta {
-				nvidia,pins = "pta";
-				nvidia,function = "rsvd4";
-			};
-		};
-	};
-
-	i2s@70002800 {
-		status = "okay";
-	};
-
-	serial@70006300 {
-		status = "okay";
-	};
-
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
-	};
-
-	i2c@7000c000 {
-		clock-frequency = <400000>;
-		status = "okay";
-	};
-
-	i2c@7000c400 {
-		clock-frequency = <100000>;
-		status = "okay";
-	};
-
-	i2cmux {
-		compatible = "i2c-mux-pinctrl";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		i2c-parent = <&{/i2c@7000c400}>;
-
-		pinctrl-names = "ddc", "pta", "idle";
-		pinctrl-0 = <&state_i2cmux_ddc>;
-		pinctrl-1 = <&state_i2cmux_pta>;
-		pinctrl-2 = <&state_i2cmux_idle>;
-
-		hdmi_ddc: i2c@0 {
-			reg = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		i2c@1 {
-			reg = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
-
-	i2c@7000d000 {
-		clock-frequency = <400000>;
-		status = "okay";
-
-		pmic: tps6586x@34 {
-			compatible = "ti,tps6586x";
-			reg = <0x34>;
-			interrupts = <0 86 0x4>;
-
-			ti,system-power-controller;
-
-			#gpio-cells = <2>;
-			gpio-controller;
-
-			sys-supply = <&vdd_5v0_reg>;
-			vin-sm0-supply = <&sys_reg>;
-			vin-sm1-supply = <&sys_reg>;
-			vin-sm2-supply = <&sys_reg>;
-			vinldo01-supply = <&sm2_reg>;
-			vinldo23-supply = <&sm2_reg>;
-			vinldo4-supply = <&sm2_reg>;
-			vinldo678-supply = <&sm2_reg>;
-			vinldo9-supply = <&sm2_reg>;
-
-			regulators {
-				sys_reg: sys {
-					regulator-name = "vdd_sys";
-					regulator-always-on;
-				};
-
-				sm0 {
-					regulator-name = "vdd_sys_sm0,vdd_core";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-always-on;
-				};
-
-				sm1 {
-					regulator-name = "vdd_sys_sm1,vdd_cpu";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-					regulator-always-on;
-				};
-
-				sm2_reg: sm2 {
-					regulator-name = "vdd_sys_sm2,vin_ldo*";
-					regulator-min-microvolt = <3700000>;
-					regulator-max-microvolt = <3700000>;
-					regulator-always-on;
-				};
-
-				ldo0 {
-					regulator-name = "vdd_ldo0,vddio_pex_clk";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-				};
-
-				ldo1 {
-					regulator-name = "vdd_ldo1,avdd_pll*";
-					regulator-min-microvolt = <1100000>;
-					regulator-max-microvolt = <1100000>;
-					regulator-always-on;
-				};
-
-				ldo2 {
-					regulator-name = "vdd_ldo2,vdd_rtc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-				};
-
-				ldo3 {
-					regulator-name = "vdd_ldo3,avdd_usb*";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
-				};
-
-				ldo4 {
-					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-				};
-
-				ldo5 {
-					regulator-name = "vdd_ldo5,vcore_mmc";
-					regulator-min-microvolt = <2850000>;
-					regulator-max-microvolt = <2850000>;
-				};
-
-				ldo6 {
-					regulator-name = "vdd_ldo6,avdd_vdac";
-					/*
-					 * According to the Tegra 2 Automotive
-					 * DataSheet, a typical value for this
-					 * would be 2.8V, but the PMIC only
-					 * supports 2.85V.
-					 */
-					regulator-min-microvolt = <2850000>;
-					regulator-max-microvolt = <2850000>;
-				};
-
-				hdmi_vdd_reg: ldo7 {
-					regulator-name = "vdd_ldo7,avdd_hdmi";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-				};
-
-				hdmi_pll_reg: ldo8 {
-					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo9 {
-					regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
-					/*
-					 * According to the Tegra 2 Automotive
-					 * DataSheet, a typical value for this
-					 * would be 2.8V, but the PMIC only
-					 * supports 2.85V.
-					 */
-					regulator-min-microvolt = <2850000>;
-					regulator-max-microvolt = <2850000>;
-					regulator-always-on;
-				};
-
-				ldo_rtc {
-					regulator-name = "vdd_rtc_out";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
-				};
-			};
-		};
-
-		temperature-sensor@4c {
-			compatible = "onnn,nct1008";
-			reg = <0x4c>;
-		};
-	};
-
-	pmc {
-		nvidia,invert-interrupt;
-	};
-
-	usb@c5008000 {
-		status = "okay";
-	};
-
-	sdhci@c8000600 {
-		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
-		bus-width = <4>;
-		status = "okay";
-	};
-
-	regulators {
-		compatible = "simple-bus";
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		vdd_5v0_reg: regulator@0 {
-			compatible = "regulator-fixed";
-			reg = <0>;
-			regulator-name = "vdd_5v0";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			regulator-always-on;
-		};
-	};
-};
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
deleted file mode 100644
index 4c1b08d..0000000
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ /dev/null
@@ -1,77 +0,0 @@
-/dts-v1/;
-
-#include "tegra20-tamonten.dtsi"
-
-/ {
-	model = "Avionic Design Tamonten Evaluation Carrier";
-	compatible = "ad,tec", "nvidia,tegra20";
-
-	aliases {
-		usb0 = "/usb@c5008000";
-		sdhci0 = "/sdhci@c8000600";
-	};
-
-	memory {
-		reg = <0x00000000 0x20000000>;
-	};
-
-	host1x {
-		status = "okay";
-
-		dc@54200000 {
-			status = "okay";
-
-			rgb {
-				nvidia,panel = <&lcd_panel>;
-				status = "okay";
-			};
-		};
-	};
-
-	serial@70006300 {
-		clock-frequency = <216000000>;
-	};
-
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		status = "disabled";
-	};
-
-	usb@c5000000 {
-		status = "disabled";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
-	};
-
-	lcd_panel: panel {
-		clock = <33260000>;
-		xres = <800>;
-		yres = <480>;
-		left-margin = <120>;
-		right-margin = <120>;
-		hsync-len = <16>;
-		lower-margin = <15>;
-		upper-margin = <15>;
-		vsync-len = <15>;
-
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 0 500000>;
-		nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
-		nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
-		nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
-		nvidia,panel-timings = <0 0 0 0>;
-	};
-};
diff --git a/board/avionic-design/dts/tegra30-tamonten.dtsi b/board/avionic-design/dts/tegra30-tamonten.dtsi
deleted file mode 100644
index 50d5762..0000000
--- a/board/avionic-design/dts/tegra30-tamonten.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-#include "tegra30.dtsi"
-
-/ {
-	model = "Avionic Design Tamonten NG";
-	compatible = "ad,tamonten-ng", "nvidia,tegra30";
-
-	memory {
-		reg = <0x80000000 0x40000000>;
-	};
-
-	aliases {
-		i2c0 = "/i2c@7000c000";
-		i2c1 = "/i2c@7000c700";
-		i2c2 = "/i2c@7000c400";
-		i2c3 = "/i2c@7000c500";
-		i2c4 = "/i2c@7000d000";
-		sdhci0 = "/sdhci@78000600";
-		sdhci1 = "/sdhci@78000400";
-		sdhci2 = "/sdhci@78000000";
-		usb0 = "/usb@7d008000";
-	};
-
-	/* GEN1 */
-	i2c@7000c000 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	/* GEN2 */
-	i2c@7000c400 {
-		clock-frequency = <100000>;
-	};
-
-	/* CAM */
-	i2c@7000c500 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	/* DDC */
-	i2c@7000c700 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	/* PWR */
-	i2c@7000d000 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	/* SD slot on the base board */
-	sdhci@78000400 {
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 67 0>; /* gpio PI3 */
-		bus-width = <4>;
-	};
-
-	/* EMMC on the COM module */
-	sdhci@78000600 {
-		status = "okay";
-		bus-width = <8>;
-	};
-
-	usb@7d008000 {
-		status = "okay";
-	};
-
-};
diff --git a/board/avionic-design/dts/tegra30-tec-ng.dts b/board/avionic-design/dts/tegra30-tec-ng.dts
deleted file mode 100644
index 8a69e81..0000000
--- a/board/avionic-design/dts/tegra30-tec-ng.dts
+++ /dev/null
@@ -1,18 +0,0 @@
-/dts-v1/;
-
-#include "tegra30-tamonten.dtsi"
-
-/ {
-	model = "Avionic Design Tamonten™ NG Evaluation Carrier";
-	compatible = "ad,tec-ng", "nvidia,tegra30";
-
-	/* GEN2 */
-	i2c@7000c400 {
-		status = "okay";
-	};
-
-	/* SD card slot */
-	sdhci@78000400 {
-		status = "okay";
-	};
-};
diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile
index 87e1912..bcf7ccf 100644
--- a/board/avionic-design/medcom-wide/Makefile
+++ b/board/avionic-design/medcom-wide/Makefile
@@ -9,4 +9,4 @@
 
 obj-y	:= ../common/tamonten.o
 
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile
index 87e1912..bcf7ccf 100644
--- a/board/avionic-design/plutux/Makefile
+++ b/board/avionic-design/plutux/Makefile
@@ -9,4 +9,4 @@
 
 obj-y	:= ../common/tamonten.o
 
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile
index 79d86026..a556b92 100644
--- a/board/avionic-design/tec-ng/Makefile
+++ b/board/avionic-design/tec-ng/Makefile
@@ -7,4 +7,4 @@
 
 obj-y	:= ../common/tamonten-ng.o
 
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile
index 87e1912..bcf7ccf 100644
--- a/board/avionic-design/tec/Makefile
+++ b/board/avionic-design/tec/Makefile
@@ -9,4 +9,4 @@
 
 obj-y	:= ../common/tamonten.o
 
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk
index f1ef9bf..0d3df2d 100644
--- a/board/bct-brettl2/config.mk
+++ b/board/bct-brettl2/config.mk
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk
index f1ef9bf..0d3df2d 100644
--- a/board/bf518f-ezbrd/config.mk
+++ b/board/bf518f-ezbrd/config.mk
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk
index f1ef9bf..0d3df2d 100644
--- a/board/bf526-ezbrd/config.mk
+++ b/board/bf526-ezbrd/config.mk
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk
index f1ef9bf..0d3df2d 100644
--- a/board/bf527-ad7160-eval/config.mk
+++ b/board/bf527-ad7160-eval/config.mk
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk
index f1ef9bf..0d3df2d 100644
--- a/board/bf527-ezkit/config.mk
+++ b/board/bf527-ezkit/config.mk
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk
index 5f327a9..af299f5 100644
--- a/board/bf527-sdp/config.mk
+++ b/board/bf527-sdp/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk
index 973d357..97eaafe 100644
--- a/board/bf533-ezkit/config.mk
+++ b/board/bf533-ezkit/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk
index 973d357..97eaafe 100644
--- a/board/bf533-stamp/config.mk
+++ b/board/bf533-stamp/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk
index ae2ea0b..bc0e747 100644
--- a/board/bf537-stamp/config.mk
+++ b/board/bf537-stamp/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk
index 973d357..97eaafe 100644
--- a/board/bf538f-ezkit/config.mk
+++ b/board/bf538f-ezkit/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk
index ad3a729..8d2c60f 100644
--- a/board/bf548-ezkit/config.mk
+++ b/board/bf548-ezkit/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk
index c33aef9..ce94715 100644
--- a/board/bf561-acvilon/config.mk
+++ b/board/bf561-acvilon/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk
index c33aef9..ce94715 100644
--- a/board/bf561-ezkit/config.mk
+++ b/board/bf561-ezkit/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c
index cfc64fe..43a4330 100644
--- a/board/bf609-ezkit/bf609-ezkit.c
+++ b/board/bf609-ezkit/bf609-ezkit.c
@@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis)
 	if (CONFIG_DW_PORTS & 1) {
 		static const unsigned short pins[] = P_RMII0;
 		if (!peripheral_request_list(pins, "emac0"))
-			ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
+			ret += designware_initialize(EMAC0_MACCFG, 0);
 	}
 	if (CONFIG_DW_PORTS & 2) {
 		static const unsigned short pins[] = P_RMII1;
 		if (!peripheral_request_list(pins, "emac1"))
-			ret += designware_initialize(1, EMAC1_MACCFG, 1, 0);
+			ret += designware_initialize(EMAC1_MACCFG, 0);
 	}
 
 	return ret;
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 3f4cfa1..d9c05b0 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -389,7 +389,7 @@ int board_eth_init(bd_t *bis)
 	}
 #endif
 
-#ifdef CONFIG_MV_UDC
+#ifdef CONFIG_CI_UDC
 	/* For otg ethernet*/
 	usb_eth_initialize(bis);
 #endif
diff --git a/board/br4/config.mk b/board/br4/config.mk
index 5c18d5c..2436ec0 100644
--- a/board/br4/config.mk
+++ b/board/br4/config.mk
@@ -9,6 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/broadcom/bcm28155_ap/Makefile b/board/broadcom/bcm28155_ap/Makefile
new file mode 100644
index 0000000..b18785a
--- /dev/null
+++ b/board/broadcom/bcm28155_ap/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= $(BOARD).o
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
new file mode 100644
index 0000000..940a1c2
--- /dev/null
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <mmc.h>
+#include <asm/kona-common/kona_sdhci.h>
+#include <asm/kona-common/clk.h>
+#include <asm/arch/sysmap.h>
+
+#define SECWATCHDOG_SDOGCR_OFFSET	0x00000000
+#define SECWATCHDOG_SDOGCR_EN_SHIFT	27
+#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT	26
+#define SECWATCHDOG_SDOGCR_CLKS_SHIFT	20
+#define SECWATCHDOG_SDOGCR_LD_SHIFT	0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+	printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	clk_init();
+
+	return 0;
+}
+
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+	/* Disable watchdog reset - watchdog unused */
+	writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) |
+	       (0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) |
+	       (4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) |
+	       (0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT),
+	       (SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET));
+
+	return 0;
+}
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_KONA_SDHCI
+/*
+ * mmc_init - Initializes mmc
+ */
+int board_mmc_init(bd_t *bis)
+{
+	int ret = 0;
+
+	/* Register eMMC - SDIO2 */
+	ret = kona_sdhci_init(1, 400000, 0);
+	if (ret)
+		return ret;
+
+	/* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
+	ret = kona_sdhci_init(3, 400000, 0);
+	return ret;
+}
+#endif
diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk
deleted file mode 100644
index 0c05dd0..0000000
--- a/board/chromebook-x86/coreboot/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
-#
-# SPDX-License-Identifier:	GPL-2.0	BSD-3-Clause
-#
-
-HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
diff --git a/board/chromebook-x86/dts/alex.dts b/board/chromebook-x86/dts/alex.dts
deleted file mode 100644
index 2f13544..0000000
--- a/board/chromebook-x86/dts/alex.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-/dts-v1/;
-
-/include/ "coreboot.dtsi"
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	model = "Google Alex";
-	compatible = "google,alex", "intel,atom-pineview";
-
-	config {
-	       silent_console = <0>;
-	};
-
-	gpio: gpio {};
-
-	serial {
-		reg = <0x3f8 8>;
-		clock-frequency = <115200>;
-	};
-
-	chosen { };
-	memory { device_type = "memory"; reg = <0 0>; };
-};
diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts
deleted file mode 100644
index 4a37dac..0000000
--- a/board/chromebook-x86/dts/link.dts
+++ /dev/null
@@ -1,35 +0,0 @@
-/dts-v1/;
-
-/include/ "coreboot.dtsi"
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	model = "Google Link";
-	compatible = "google,link", "intel,celeron-ivybridge";
-
-	config {
-	       silent_console = <0>;
-	};
-
-	gpio: gpio {};
-
-	serial {
-		reg = <0x3f8 8>;
-		clock-frequency = <115200>;
-	};
-
-	chosen { };
-	memory { device_type = "memory"; reg = <0 0>; };
-
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich9";
-		spi-flash@0 {
-			reg = <0>;
-			compatible = "winbond,w25q64", "spi-flash";
-			memory-map = <0xff800000 0x00800000>;
-		};
-	};
-};
diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk
index f1ef9bf..0d3df2d 100644
--- a/board/cm-bf527/config.mk
+++ b/board/cm-bf527/config.mk
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk
index 973d357..97eaafe 100644
--- a/board/cm-bf533/config.mk
+++ b/board/cm-bf533/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk
index 973d357..97eaafe 100644
--- a/board/cm-bf537e/config.mk
+++ b/board/cm-bf537e/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk
index 973d357..97eaafe 100644
--- a/board/cm-bf537u/config.mk
+++ b/board/cm-bf537u/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk
index c005afb..289c8a4 100644
--- a/board/cm-bf548/config.mk
+++ b/board/cm-bf548/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
index a43413e..c35d285 100644
--- a/board/cm-bf548/video.c
+++ b/board/cm-bf548/video.c
@@ -11,6 +11,7 @@
 #include <config.h>
 #include <malloc.h>
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/gpio.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/dma.h>
diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk
index c33aef9..ce94715 100644
--- a/board/cm-bf561/config.mk
+++ b/board/cm-bf561/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
index 2511928..8315a57 100644
--- a/board/cm4008/flash.c
+++ b/board/cm4008/flash.c
@@ -57,7 +57,7 @@ unsigned long flash_init (void)
 	 */
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_SYS_FLASH_BASE,
-		       CONFIG_SYS_FLASH_BASE + _bss_start_ofs,
+		       CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
 		       &flash_info[0]);
 
 	return size;
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
index 2511928..8315a57 100644
--- a/board/cm41xx/flash.c
+++ b/board/cm41xx/flash.c
@@ -57,7 +57,7 @@ unsigned long flash_init (void)
 	 */
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_SYS_FLASH_BASE,
-		       CONFIG_SYS_FLASH_BASE + _bss_start_ofs,
+		       CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
 		       &flash_info[0]);
 
 	return size;
diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts
deleted file mode 100644
index 780203c..0000000
--- a/board/compal/dts/tegra20-paz00.dts
+++ /dev/null
@@ -1,91 +0,0 @@
-/dts-v1/;
-
-#include "tegra20.dtsi"
-
-/ {
-	model = "Toshiba AC100 / Dynabook AZ";
-	compatible = "compal,paz00", "nvidia,tegra20";
-
-	aliases {
-		usb0 = "/usb@c5008000";
-		sdhci0 = "/sdhci@c8000600";
-		sdhci1 = "/sdhci@c8000000";
-	};
-
-	memory {
-		reg = <0x00000000 0x20000000>;
-	};
-
-	host1x {
-		status = "okay";
-		dc@54200000 {
-			status = "okay";
-			rgb {
-				status = "okay";
-				nvidia,panel = <&lcd_panel>;
-			};
-		};
-	};
-
-	serial@70006000 {
-		clock-frequency = < 216000000 >;
-	};
-
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		status = "disabled";
-	};
-
-	usb@c5000000 {
-		status = "disabled";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
-	};
-
-	sdhci@c8000000 {
-		status = "okay";
-		cd-gpios = <&gpio 173 1>; /* gpio PV5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 169 0>; /* gpio PV1 */
-		bus-width = <4>;
-	};
-
-	sdhci@c8000600 {
-		status = "okay";
-		bus-width = <8>;
-	};
-
-	lcd_panel: panel {
-		/* PAZ00 has 1024x600 */
-		clock = <54030000>;
-		xres = <1024>;
-		yres = <600>;
-		right-margin = <160>;
-		left-margin = <24>;
-		hsync-len = <136>;
-		upper-margin = <3>;
-		lower-margin = <61>;
-		vsync-len = <6>;
-		hsync-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 0 0>;
-		nvidia,backlight-enable-gpios = <&gpio 164 0>;	/* PU4 */
-		nvidia,lvds-shutdown-gpios = <&gpio 102 0>;	/* PM6 */
-		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
-		nvidia,panel-vdd-gpios = <&gpio 4 0>;		/* PA4 */
-		nvidia,panel-timings = <400 4 203 17 15>;
-	};
-};
diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile
index b2d3b6b..e6a0b29 100644
--- a/board/compal/paz00/Makefile
+++ b/board/compal/paz00/Makefile
@@ -16,4 +16,4 @@
 
 obj-y	:= paz00.o
 
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
index 01019e8..9583149 100644
--- a/board/compulab/cm_t335/cm_t335.c
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -47,7 +47,7 @@ static void cpsw_control(int enabled)
 static struct cpsw_slave_data cpsw_slave = {
 	.slave_reg_ofs	= 0x208,
 	.sliver_reg_ofs	= 0xd80,
-	.phy_id		= 0,
+	.phy_addr	= 0,
 	.phy_if		= PHY_INTERFACE_MODE_RGMII,
 };
 
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
index 1b609a2..0984dfe 100644
--- a/board/compulab/cm_t335/u-boot.lds
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -61,7 +61,12 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 	/*
 	 * Deprecated: this MMU section is used by pxa at present but
@@ -92,10 +97,14 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.hash : { *(.hash) }
+	.got.plt : { *(.got.plt) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts
deleted file mode 100644
index ee31476..0000000
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ /dev/null
@@ -1,64 +0,0 @@
-/dts-v1/;
-
-#include "tegra20.dtsi"
-
-/ {
-	model = "Compulab TrimSlice board";
-	compatible = "compulab,trimslice", "nvidia,tegra20";
-
-	aliases {
-		usb0 = "/usb@c5008000";
-		usb1 = "/usb@c5000000";
-		sdhci0 = "/sdhci@c8000600";
-		sdhci1 = "/sdhci@c8000000";
-	};
-
-	memory {
-		reg = <0x00000000 0x40000000>;
-	};
-
-	serial@70006000 {
-		clock-frequency = <216000000>;
-	};
-
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
-	spi@7000c380 {
-		status = "okay";
-		spi-max-frequency = <25000000>;
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		status = "disabled";
-	};
-
-	usb@c5000000 {
-		nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
-	};
-
-	usb@c5004000 {
-		status = "disabled";
-	};
-
-	sdhci@c8000000 {
-		status = "okay";
-		bus-width = <4>;
-	};
-
-	sdhci@c8000600 {
-		status = "okay";
-		cd-gpios = <&gpio 121 1>; /* gpio PP1 */
-		wp-gpios = <&gpio 122 0>; /* gpio PP2 */
-		bus-width = <4>;
-	};
-};
diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile
index f3bd00d..311eb92 100644
--- a/board/compulab/trimslice/Makefile
+++ b/board/compulab/trimslice/Makefile
@@ -7,4 +7,4 @@
 
 obj-y	:= trimslice.o
 
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile
index 5f6c690..63f43da 100644
--- a/board/cray/L1/Makefile
+++ b/board/cray/L1/Makefile
@@ -9,8 +9,10 @@ obj-y	= L1.o flash.o
 obj-y	+= init.o
 obj-y	+= bootscript.o
 
-$(obj)bootscript.c: $(obj)bootscript.image
-	od -t x1 -v -A x $^ | awk -f x2c.awk > $@
+$(obj)/bootscript.c: $(obj)/bootscript.image
+	od -t x1 -v -A x $^ | awk -f $(srctree)/$(src)/x2c.awk > $@
 
-$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile
-	-$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@
+$(obj)/bootscript.image: $(src)/bootscript.hush
+	-$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $< $@
+
+clean-files := bootscript.c bootscript.image
\ No newline at end of file
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index 5480d1f..de21a13 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -49,5 +49,9 @@ SECTIONS
 	} >.sram
 
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
 }
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index d49c314..299226b 100644
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -61,5 +61,8 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
 }
diff --git a/board/dvlhost/Makefile b/board/dvlhost/Makefile
deleted file mode 100644
index 8b48936..0000000
--- a/board/dvlhost/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dvlhost.o watchdog.o
diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c
deleted file mode 100644
index 087070f..0000000
--- a/board/dvlhost/dvlhost.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "dvlhost_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* CS1: LED Latch */
-	writel(0xBFFF0002, IXP425_EXP_CS1);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	/* Setup GPIOs used as output */
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST);
-
-	/*
-	 * LED latch enable and watchdog enable are tied to the same GPIO,
-	 * so we need to trigger the watchdog if we want to enable the LEDs.
-	*/
-#ifdef CONFIG_HW_WATCHDOG
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN);
-#else
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN);
-#endif
-
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST);
-
-	/* Setup GPIOs for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB);
-
-	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
-
-	/* turn off all LEDs */
-	writew(0x0000, DVLHOST_LED_LATCH);
-
-	udelay(533);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST);
-
-	return 0;
-}
-
-/* Check Board Identity */
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	puts("Board: dLAN 200AV (dvlhost)");
-
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_ixp_init(&hose);
-}
-#endif
-
-void reset_phy(void)
-{
-	/* init IcPlus IP175C ethernet switch to native IP175C mode */
-	miiphy_write("NPE1", 29, 31, 0x175C);
-}
diff --git a/board/dvlhost/dvlhost_hw.h b/board/dvlhost/dvlhost_hw.h
deleted file mode 100644
index 545099e..0000000
--- a/board/dvlhost/dvlhost_hw.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the
- * dLAN200 AV Wireless G ("dvlhost") board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _DVLHOST_HW_H
-#define _DVLHOST_HW_H
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_WDGTRIGGER	0 /* Out */
-#define CONFIG_SYS_GPIO_BTN_WLAN	1
-#define CONFIG_SYS_GPIO_BTN_PAIRING	6
-#define CONFIG_SYS_GPIO_DLAN_PAIRING	7 /* Out */
-#define CONFIG_SYS_GPIO_BTN_RESET	9
-#define CONFIG_SYS_GPIO_IRQB		10
-#define CONFIG_SYS_GPIO_IRQA		11
-#define CONFIG_SYS_GPIO_WDG_LED_EN	12 /* Out */
-#define CONFIG_SYS_GPIO_PCIRST		13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK	15 /* Out */
-
-#define DVLHOST_LED_LATCH	IXP425_EXP_BUS_CS1_BASE_PHYS
-
-#endif
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
deleted file mode 100644
index ebcaf44..0000000
--- a/board/dvlhost/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN (4);
-	.text : {
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		net/built-in.o(.text*)
-		board/dvlhost/built-in.o(.text*)
-		arch/arm/cpu/ixp/built-in.o(.text*)
-		drivers/serial/built-in.o(.text*)
-
-		. = env_offset;
-		common/env_embedded.o(.ppcenv)
-		*(.text*)
-	}
-
-	. = ALIGN (4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN (4);
-	.data : {
-		*(.data*)
-	}
-	. = ALIGN (4);
-	.got : {
-		*(.got)
-	}
-	. =.;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN (4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	.dynsym _end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/dvlhost/watchdog.c b/board/dvlhost/watchdog.c
deleted file mode 100644
index 02ec35e..0000000
--- a/board/dvlhost/watchdog.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include "dvlhost_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#include <asm/arch/ixp425.h>
-
-void hw_watchdog_reset(void)
-{
-	unsigned int x;
-	x = readl(IXP425_GPIO_GPOUTR);
-	x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER));
-	writel(x, IXP425_GPIO_GPOUTR);
-}
-
-#endif /* CONFIG_HW_WATCHDOG */
diff --git a/board/fads/fads.h b/board/fads/fads.h
index cf6c928..fa49080 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -127,8 +127,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
index 3cfdb72..2111711 100644
--- a/board/freescale/c29xpcie/spl.c
+++ b/board/freescale/c29xpcie/spl.c
@@ -12,7 +12,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-ulong get_effective_memsize(void)
+phys_size_t get_effective_memsize(void)
 {
 	return CONFIG_SYS_L2_SIZE;
 }
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 25f063d..f6a0879 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -13,7 +13,10 @@ MINIMAL=y
 endif
 endif
 
-ifndef MINIMAL
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
 obj-$(CONFIG_FSL_CADMUS)	+= cadmus.o
 obj-$(CONFIG_FSL_VIA)		+= cds_via.o
 obj-$(CONFIG_FMAN_ENET)	+= fman.o
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 1cca176..6da1d4b 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -69,7 +69,12 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 /*
  * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
@@ -90,7 +95,7 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
-	.dynsym _end : { *(.dynsym) }
+	.dynsym _image_binary_end : { *(.dynsym) }
 	.dynbss : { *(.dynbss) }
 	.dynstr : { *(.dynstr*) }
 	.dynamic : { *(.dynamic*) }
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index db0bf17..08dd66f 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -343,6 +343,7 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
 	u32 cpurev;
@@ -356,6 +357,7 @@ int print_cpuinfo(void)
 	printf("Reset cause: %s\n", get_reset_cause());
 	return 0;
 }
+#endif
 
 /*
  * Do not overwrite the console
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index d6f05f3..660d1bb 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -18,6 +18,10 @@ obj-y	+= spl_minimal.o tlb.o law.o
 
 else
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
 obj-y	+= p1010rdb.o
 obj-y	+= ddr.o
 obj-y	+= law.o
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
new file mode 100644
index 0000000..11bd9cf
--- /dev/null
+++ b/board/freescale/p1010rdb/spl.c
@@ -0,0 +1,108 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+	console_init_f();
+
+	/* Clock configuration to access CPLD using IFC(GPCM) */
+	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+#ifdef CONFIG_P1010RDB_PB
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	*/
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+			    gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+#else
+	env_relocate();
+#endif
+
+	i2c_init_all();
+
+	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("\nTertiary program loader running in sram...");
+#else
+	puts("\nSecond program loader running in sram...");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index 39a5a0f..6079570 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -16,78 +16,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-
-void sdram_init(void)
-{
-	struct ccsr_ddr __iomem *ddr =
-		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	u32 ddr_ratio;
-	unsigned long ddr_freq_mhz;
-
-	ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-	ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-	ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000;
-
-	/* mask off E bit */
-	u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
-	if (ddr_freq_mhz < 700) {
-		__raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
-		__raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
-		__raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
-		__raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
-		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
-		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
-	} else {
-		__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
-		__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
-		__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
-		__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
-		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
-		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
-	}
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
-	/* P1014 and it's derivatives support max 16bit DDR width */
-	if (svr == SVR_P1014) {
-		__raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
-		__raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
-		/* For CS0_BNDS we divide the start and end address by 2, so we can just
-		 * shift the entire register to achieve the desired result and the mask
-		 * the value so we don't write reserved fields */
-		__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
-	}
-
-	asm volatile("sync;isync");
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
-	set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
 	/* initialize selected port with appropriate baud rate */
 	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
@@ -98,9 +36,6 @@ void board_init_f(ulong bootflag)
 
 	puts("\nNAND boot... ");
 
-	/* Initialize the DDR3 */
-	sdram_init();
-
 	/* copy code to RAM and jump to it - this should not return */
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
@@ -111,6 +46,7 @@ void board_init_f(ulong bootflag)
 
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
+	puts("\nSecond program loader running in sram...");
 	nand_boot();
 }
 
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index a3d36b3..af40f97 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -73,10 +73,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 8, BOOKE_PAGESZ_1G, 1)
+			0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1)
 #endif
 };
 
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 7f151e3..7bd9d29 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -21,7 +21,7 @@ static const u32 sysclk_tbl[] = {
 	99999000, 11111000, 12499800, 13333200
 };
 
-ulong get_effective_memsize(void)
+phys_size_t get_effective_memsize(void)
 {
 	return CONFIG_SYS_L2_SIZE;
 }
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 9bb0716..8d0d850 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -20,7 +20,7 @@ static const u32 sysclk_tbl[] = {
 	99999000, 11111000, 12499800, 13333200
 };
 
-ulong get_effective_memsize(void)
+phys_size_t get_effective_memsize(void)
 {
 	return CONFIG_SYS_L2_SIZE;
 }
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
index 93af9eb..c7470d7 100644
--- a/board/freescale/t1040qds/Makefile
+++ b/board/freescale/t1040qds/Makefile
@@ -9,3 +9,4 @@ obj-y	+= ddr.o
 obj-$(CONFIG_PCI)     += pci.o
 obj-y	+= law.o
 obj-y	+= tlb.o
+obj-y	+= eth.o
diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README
index 6d380ae..8160ca0 100644
--- a/board/freescale/t1040qds/README
+++ b/board/freescale/t1040qds/README
@@ -121,14 +121,14 @@ NOR Flash memory Map on T1040QDS
 0xEFF40000      0xEFFFFFFF      u-boot (current bank)            768KB
 0xEFF20000      0xEFF3FFFF      u-boot env (current bank)        128KB
 0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
-0xED300000      0xEFF3FFFF      rootfs (alt bank)                44MB + 256KB
-0xEC800000      0xEC8FFFF       Hardware device tree (alt bank)  1MB
+0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
+0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
 0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
 0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
 0xEBF40000      0xEBFFFFFF      u-boot (alt bank)                768KB
 0xEBF20000      0xEBF3FFFF      u-boot env (alt bank)            128KB
 0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
-0xE9300000      0xEBF3FFFF      rootfs (current bank)            44MB + 256KB
+0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
 0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
 0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
 0xE8000000      0xE801FFFF      RCW (current bank)               128KB
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
new file mode 100644
index 0000000..3077b4a
--- /dev/null
+++ b/board/freescale/t1040qds/eth.c
@@ -0,0 +1,492 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * The RGMII PHYs are provided by the two on-board PHY connected to
+ * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
+ * PHY or by the standard four-port SGMII riser card (VSC).
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/fman.h"
+#include "../common/qixis.h"
+
+#include "t1040qds_qixis.h"
+
+#ifdef CONFIG_FMAN_ENET
+ /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
+ *   Bank 1 -> Lanes A, B, C, D
+ *   Bank 2 -> Lanes E, F, G, H
+ */
+
+ /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
+  * means that the mapping must be determined dynamically, or that the lane
+  * maps to something other than a board slot.
+  */
+static u8 lane_to_slot[] = {
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+static int riser_phy_addr[] = {
+	CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE	0xFFFFFFFF
+#define EMI1_RGMII0	0
+#define EMI1_RGMII1	1
+#define EMI1_SLOT1	2
+#define EMI1_SLOT3	3
+#define EMI1_SLOT4	4
+#define EMI1_SLOT5	5
+#define EMI1_SLOT6	6
+#define EMI1_SLOT7	7
+#define EMI2		8
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+	"T1040_QDS_MDIO0",
+	"T1040_QDS_MDIO1",
+	"T1040_QDS_MDIO2",
+	"T1040_QDS_MDIO3",
+	"T1040_QDS_MDIO4",
+	"T1040_QDS_MDIO5",
+	"T1040_QDS_MDIO6",
+	"T1040_QDS_MDIO7",
+};
+
+struct t1040_qds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = t1040_qds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+static void t1040_qds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+	if (muxval <= 7) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct t1040_qds_mdio *priv = bus->priv;
+
+	t1040_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct t1040_qds_mdio *priv = bus->priv;
+
+	t1040_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t1040_qds_mdio_reset(struct mii_dev *bus)
+{
+	struct t1040_qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct t1040_qds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate t1040_qds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate t1040_qds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = t1040_qds_mdio_read;
+	bus->write = t1040_qds_mdio_write;
+	bus->reset = t1040_qds_mdio_reset;
+	sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+
+	return mdio_register(bus);
+}
+
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the T1040QDS board the mapping is controlled by ?? register.
+ */
+static void initialize_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
+		>> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	QIXIS_WRITE(cms[0], 0x07);
+
+	switch (serdes1_prtcl) {
+	case 0x60:
+	case 0x66:
+	case 0x67:
+	case 0x69:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 6;
+		lane_to_slot[3] = 5;
+		break;
+	case 0x86:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		break;
+	case 0x87:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[7] = 7;
+		break;
+	case 0x89:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[7] = 7;
+		break;
+	case 0x8d:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0x8F:
+	case 0x85:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 6;
+		lane_to_slot[3] = 5;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xA5:
+		lane_to_slot[1] = 7;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xA7:
+		lane_to_slot[1] = 7;
+		lane_to_slot[7] = 7;
+		break;
+	case 0xAA:
+		lane_to_slot[1] = 7;
+		lane_to_slot[6] = 7;
+		lane_to_slot[7] = 7;
+		break;
+	case 0x40:
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		break;
+	default:
+		printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	}
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port.
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used, and we recalculate the offset anyway.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ *
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	phy_interface_t intf = fm_info_get_enet_if(port);
+	char phy[16];
+
+	/* The RGMII PHY is identified by the MAC connected to it */
+	if (intf == PHY_INTERFACE_MODE_RGMII) {
+		sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
+		fdt_set_phy_handle(fdt, compat, addr, phy);
+	}
+
+	/* The SGMII PHY is identified by the MAC connected to it */
+	if (intf == PHY_INTERFACE_MODE_SGMII) {
+		int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
+						 + port);
+		u8 slot;
+		if (lane < 0)
+			return;
+		slot = lane_to_slot[lane];
+		if (slot) {
+			/* Slot housing a SGMII riser card */
+			sprintf(phy, "phy_s%x_%02x", slot,
+				(fm_info_get_phy_address(port - FM1_DTSEC1)-
+				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
+			fdt_set_phy_handle(fdt, compat, addr, phy);
+		}
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i, lane, idx;
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+						     SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+
+			switch (mdio_mux[i]) {
+			case EMI1_SLOT3:
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+				break;
+			case EMI1_SLOT5:
+				fdt_status_okay_by_alias(fdt, "emi1_slot5");
+				break;
+			case EMI1_SLOT6:
+				fdt_status_okay_by_alias(fdt, "emi1_slot6");
+				break;
+			case EMI1_SLOT7:
+				fdt_status_okay_by_alias(fdt, "emi1_slot7");
+				break;
+			}
+		break;
+		case PHY_INTERFACE_MODE_RGMII:
+			if (i == FM1_DTSEC4)
+				fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
+
+			if (i == FM1_DTSEC5)
+				fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+			break;
+		default:
+			break;
+		}
+	}
+}
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+static void set_brdcfg9_for_gtx_clk(void)
+{
+	u8 brdcfg9;
+	brdcfg9 = QIXIS_READ(brdcfg[9]);
+	brdcfg9 |= (1 << 5);
+	QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+void t1040_handle_phy_interface_sgmii(int i)
+{
+	int lane, idx, slot;
+	idx = i - FM1_DTSEC1;
+	lane = serdes_get_first_lane(FSL_SRDS_1,
+			SGMII_FM1_DTSEC1 + idx);
+
+	if (lane < 0)
+		return;
+	slot = lane_to_slot[lane];
+
+	switch (slot) {
+	case 1:
+		mdio_mux[i] = EMI1_SLOT1;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 3:
+		if (FM1_DTSEC4 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[0]);
+		if (FM1_DTSEC5 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[1]);
+
+		mdio_mux[i] = EMI1_SLOT3;
+
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 4:
+		mdio_mux[i] = EMI1_SLOT4;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 5:
+		/* Slot housing a SGMII riser card? */
+		fm_info_set_phy_address(i, riser_phy_addr[0]);
+		mdio_mux[i] = EMI1_SLOT5;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 6:
+		/* Slot housing a SGMII riser card? */
+		fm_info_set_phy_address(i, riser_phy_addr[0]);
+		mdio_mux[i] = EMI1_SLOT6;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 7:
+		if (FM1_DTSEC1 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[0]);
+		if (FM1_DTSEC2 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[1]);
+		if (FM1_DTSEC3 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[2]);
+
+		mdio_mux[i] = EMI1_SLOT7;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	default:
+		break;
+	}
+	fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+}
+void t1040_handle_phy_interface_rgmii(int i)
+{
+	fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
+			CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
+			CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+	mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
+		EMI1_RGMII0;
+	fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info memac_mdio_info;
+	unsigned int i;
+
+	printf("Initializing Fman\n");
+	set_brdcfg9_for_gtx_clk();
+
+	initialize_lane_to_slot();
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &memac_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+
+	/*
+	 * Program on board RGMII PHY addresses. If the SGMII Riser
+	 * card used, we'll override the PHY address later. For any DTSEC that
+	 * is RGMII, we'll also override its PHY address later. We assume that
+	 * DTSEC4 and DTSEC5 are used for RGMII.
+	 */
+	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_QSGMII:
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			t1040_handle_phy_interface_sgmii(i);
+			break;
+
+		case PHY_INTERFACE_MODE_RGMII:
+			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
+			t1040_handle_phy_interface_rgmii(i);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index de3ea5c..3dec447 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -223,6 +223,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
 #endif
 }
 
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
index 76c0c94..e51fb7a 100644
--- a/board/freescale/t104xrdb/Makefile
+++ b/board/freescale/t104xrdb/Makefile
@@ -7,6 +7,7 @@
 
 obj-y	+= t104xrdb.o
 obj-y	+= ddr.o
+obj-y	+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 obj-y	+= law.o
 obj-y	+= tlb.o
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
index 11e03bd..1da52bb 100644
--- a/board/freescale/t104xrdb/README
+++ b/board/freescale/t104xrdb/README
@@ -164,14 +164,14 @@ NOR Flash memory Map
 0xEFF40000      0xEFFFFFFF      u-boot (current bank)            768KB
 0xEFF20000      0xEFF3FFFF      u-boot env (current bank)        128KB
 0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
-0xED300000      0xEFF3FFFF      rootfs (alt bank)                44MB + 256KB
-0xEC800000      0xEC8FFFF       Hardware device tree (alt bank)  1MB
+0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
+0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
 0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
 0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
 0xEBF40000      0xEBFFFFFF      u-boot (alt bank)                768KB
 0xEBF20000      0xEBF3FFFF      u-boot env (alt bank)            128KB
 0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
-0xE9300000      0xEBF3FFFF      rootfs (current bank)            44MB + 256KB
+0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
 0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
 0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
 0xE8000000      0xE801FFFF      RCW (current bank)               128KB
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
new file mode 100644
index 0000000..0188fd4
--- /dev/null
+++ b/board/freescale/t104xrdb/eth.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info memac_mdio_info;
+	unsigned int i;
+	int phy_addr = 0;
+	printf("Initializing Fman\n");
+
+	memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &memac_mdio_info);
+
+	/*
+	 * Program on board RGMII, SGMII PHY addresses.
+	 */
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+#ifdef CONFIG_T1040RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1040RDB only supports SGMII on DTSEC3 */
+			fm_info_set_phy_address(FM1_DTSEC3,
+						CONFIG_SYS_SGMII1_PHY_ADDR);
+#endif
+		case PHY_INTERFACE_MODE_RGMII:
+			if (FM1_DTSEC4 == i)
+				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+			if (FM1_DTSEC5 == i)
+				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+		case PHY_INTERFACE_MODE_QSGMII:
+			fm_info_set_phy_address(i, 0);
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+		fm_info_set_mdio(i,
+				 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+	}
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t208xqds/Makefile
index 0b8747b..947b7f7 100644
--- a/board/freescale/t2080qds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -4,8 +4,10 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
-obj-$(CONFIG_T2080QDS) += t2080qds.o
-obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
+obj-$(CONFIG_T2080QDS) += t208xqds.o
+obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o
+obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
 obj-$(CONFIG_PCI)      += pci.o
 obj-y   += ddr.o
 obj-y   += law.o
diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t208xqds/ddr.c
index ed1334d..ed1334d 100644
--- a/board/freescale/t2080qds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t208xqds/ddr.h
index 9fc879a..9fc879a 100644
--- a/board/freescale/t2080qds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 3e4ab8f..7d8411b 100644
--- a/board/freescale/t2080qds/eth_t2080qds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -25,21 +25,30 @@
 #include <asm/fsl_serdes.h>
 #include "../common/qixis.h"
 #include "../common/fman.h"
-#include "t2080qds_qixis.h"
+#include "t208xqds_qixis.h"
 
 #define EMI_NONE	0xFFFFFFFF
 #define EMI1_RGMII1	0
 #define EMI1_RGMII2     1
 #define EMI1_SLOT1	2
+#if defined(CONFIG_T2080QDS)
 #define EMI1_SLOT2	6
 #define EMI1_SLOT3	3
 #define EMI1_SLOT4	4
 #define EMI1_SLOT5	5
-#define EMI2		7
+#elif defined(CONFIG_T2081QDS)
+#define EMI1_SLOT2      3
+#define EMI1_SLOT3      4
+#define EMI1_SLOT5      5
+#define EMI1_SLOT6      6
+#define EMI1_SLOT7      7
+#endif
+#define EMI2		8
 
 static int mdio_mux[NUM_FM_PORTS];
 
 static const char * const mdio_names[] = {
+#if defined(CONFIG_T2080QDS)
 	"T2080QDS_MDIO_RGMII1",
 	"T2080QDS_MDIO_RGMII2",
 	"T2080QDS_MDIO_SLOT1",
@@ -48,12 +57,27 @@ static const char * const mdio_names[] = {
 	"T2080QDS_MDIO_SLOT5",
 	"T2080QDS_MDIO_SLOT2",
 	"T2080QDS_MDIO_10GC",
+#elif defined(CONFIG_T2081QDS)
+	"T2081QDS_MDIO_RGMII1",
+	"T2081QDS_MDIO_RGMII2",
+	"T2081QDS_MDIO_SLOT1",
+	"T2081QDS_MDIO_SLOT2",
+	"T2081QDS_MDIO_SLOT3",
+	"T2081QDS_MDIO_SLOT5",
+	"T2081QDS_MDIO_SLOT6",
+	"T2081QDS_MDIO_SLOT7",
+	"T2081QDS_MDIO_10GC",
+#endif
 };
 
 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+#if defined(CONFIG_T2080QDS)
 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+#elif defined(CONFIG_T2081QDS)
+static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
+#endif
 
-static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
+static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
 {
 	return mdio_names[muxval];
 }
@@ -61,7 +85,7 @@ static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 {
 	struct mii_dev *bus;
-	const char *name = T2080qds_mdio_name_for_muxval(muxval);
+	const char *name = t208xqds_mdio_name_for_muxval(muxval);
 
 	if (!name) {
 		printf("No bus for muxval %x\n", muxval);
@@ -78,15 +102,15 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval)
 	return bus;
 }
 
-struct T2080qds_mdio {
+struct t208xqds_mdio {
 	u8 muxval;
 	struct mii_dev *realbus;
 };
 
-static void T2080qds_mux_mdio(u8 muxval)
+static void t208xqds_mux_mdio(u8 muxval)
 {
 	u8 brdcfg4;
-	if (muxval < 7) {
+	if (muxval < 8) {
 		brdcfg4 = QIXIS_READ(brdcfg[4]);
 		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
@@ -94,54 +118,54 @@ static void T2080qds_mux_mdio(u8 muxval)
 	}
 }
 
-static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
 				int regnum)
 {
-	struct T2080qds_mdio *priv = bus->priv;
+	struct t208xqds_mdio *priv = bus->priv;
 
-	T2080qds_mux_mdio(priv->muxval);
+	t208xqds_mux_mdio(priv->muxval);
 
 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
 }
 
-static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
 				int regnum, u16 value)
 {
-	struct T2080qds_mdio *priv = bus->priv;
+	struct t208xqds_mdio *priv = bus->priv;
 
-	T2080qds_mux_mdio(priv->muxval);
+	t208xqds_mux_mdio(priv->muxval);
 
 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 }
 
-static int T2080qds_mdio_reset(struct mii_dev *bus)
+static int t208xqds_mdio_reset(struct mii_dev *bus)
 {
-	struct T2080qds_mdio *priv = bus->priv;
+	struct t208xqds_mdio *priv = bus->priv;
 
 	return priv->realbus->reset(priv->realbus);
 }
 
-static int T2080qds_mdio_init(char *realbusname, u8 muxval)
+static int t208xqds_mdio_init(char *realbusname, u8 muxval)
 {
-	struct T2080qds_mdio *pmdio;
+	struct t208xqds_mdio *pmdio;
 	struct mii_dev *bus = mdio_alloc();
 
 	if (!bus) {
-		printf("Failed to allocate T2080QDS MDIO bus\n");
+		printf("Failed to allocate t208xqds MDIO bus\n");
 		return -1;
 	}
 
 	pmdio = malloc(sizeof(*pmdio));
 	if (!pmdio) {
-		printf("Failed to allocate T2080QDS private data\n");
+		printf("Failed to allocate t208xqds private data\n");
 		free(bus);
 		return -1;
 	}
 
-	bus->read = T2080qds_mdio_read;
-	bus->write = T2080qds_mdio_write;
-	bus->reset = T2080qds_mdio_reset;
-	sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
+	bus->read = t208xqds_mdio_read;
+	bus->write = t208xqds_mdio_write;
+	bus->reset = t208xqds_mdio_reset;
+	sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
 
 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 
@@ -154,7 +178,6 @@ static int T2080qds_mdio_init(char *realbusname, u8 muxval)
 
 	pmdio->muxval = muxval;
 	bus->priv = pmdio;
-
 	return mdio_register(bus);
 }
 
@@ -173,13 +196,20 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 		phy = fm_info_get_phy_address(port);
 		switch (port) {
+#if defined(CONFIG_T2080QDS)
 		case FM1_DTSEC1:
 		case FM1_DTSEC2:
 		case FM1_DTSEC9:
 		case FM1_DTSEC10:
-			sprintf(alias, "phy_sgmii_s3_%x", phy);
-			fdt_set_phy_handle(fdt, compat, addr, alias);
-			fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			} else if (mdio_mux[port] == EMI1_SLOT3) {
+				sprintf(alias, "phy_sgmii_s3_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			}
 			break;
 		case FM1_DTSEC5:
 		case FM1_DTSEC6:
@@ -193,6 +223,36 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_status_okay_by_alias(fdt, "emi1_slot2");
 			}
 			break;
+#elif defined(CONFIG_T2081QDS)
+		case FM1_DTSEC1:
+		case FM1_DTSEC2:
+		case FM1_DTSEC5:
+		case FM1_DTSEC6:
+		case FM1_DTSEC9:
+		case FM1_DTSEC10:
+			if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			} else if (mdio_mux[port] == EMI1_SLOT3) {
+				sprintf(alias, "phy_sgmii_s3_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			} else if (mdio_mux[port] == EMI1_SLOT5) {
+				sprintf(alias, "phy_sgmii_s5_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot5");
+			} else if (mdio_mux[port] == EMI1_SLOT6) {
+				sprintf(alias, "phy_sgmii_s6_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot6");
+			} else if (mdio_mux[port] == EMI1_SLOT7) {
+				sprintf(alias, "phy_sgmii_s7_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot7");
+			}
+			break;
+#endif
 		default:
 			break;
 		}
@@ -226,8 +286,8 @@ void fdt_fixup_board_enet(void *fdt)
 }
 
 /*
- * This function reads RCW to check if Serdes1{E,F,G,H} is configured
- * as slot 1/2/3 and update the lane_to_slot[] array accordingly
+ * This function reads RCW to check if Serdes1{A:H} is configured
+ * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
  */
 static void initialize_lane_to_slot(void)
 {
@@ -238,6 +298,7 @@ static void initialize_lane_to_slot(void)
 	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	switch (srds_s1) {
+#if defined(CONFIG_T2080QDS)
 	case 0x51:
 	case 0x5f:
 	case 0x65:
@@ -264,6 +325,31 @@ static void initialize_lane_to_slot(void)
 		lane_to_slot[6] = 3;
 		lane_to_slot[7] = 3;
 		break;
+#elif defined(CONFIG_T2081QDS)
+	case 0x6b:
+		lane_to_slot[4] = 1;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xca:
+	case 0xcb:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 6;
+		lane_to_slot[3] = 5;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xf2:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[5] = 4;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 7;
+		break;
+#endif
 	default:
 		break;
 	}
@@ -305,14 +391,20 @@ int board_eth_init(bd_t *bis)
 	fm_memac_mdio_init(bis, &tgec_mdio_info);
 
 	/* Register the muxing front-ends to the MDIO buses */
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-	T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+#if defined(CONFIG_T2080QDS)
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+#endif
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+#if defined(CONFIG_T2081QDS)
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+#endif
+	t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 
 	/* Set the two on-board RGMII PHY address */
 	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
@@ -327,21 +419,21 @@ int board_eth_init(bd_t *bis)
 	case 0x95:
 	case 0xa2:
 	case 0x94:
-		/* SGMII in Slot3 */
+		/* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
 		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
 	case 0x51:
 	case 0x5f:
 	case 0x65:
-		/* XAUI/HiGig in Slot3 */
+		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-		/* SGMII in Slot2 */
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
@@ -365,7 +457,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_10GEC2, 5);
 		fm_info_set_phy_address(FM1_10GEC3, 6);
 		fm_info_set_phy_address(FM1_10GEC4, 7);
-		/* SGMII in Slot2 */
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 		break;
@@ -373,7 +465,7 @@ int board_eth_init(bd_t *bis)
 	case 0x6d:
 		fm_info_set_phy_address(FM1_10GEC1, 4);
 		fm_info_set_phy_address(FM1_10GEC2, 5);
-		/* SGMII in Slot3 */
+		/* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
@@ -408,6 +500,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
+#if defined(CONFIG_T2080QDS)
 	case 0xd9:
 	case 0xd3:
 	case 0xcb:
@@ -419,6 +512,27 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 		break;
+#elif defined(CONFIG_T2081QDS)
+	case 0xca:
+	case 0xcb:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		/* SGMII in Slot5 */
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+		/* SGMII in Slot6 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		/* SGMII in Slot7 */
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		break;
+#endif
+	case 0xf2:
+		/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
 	default:
 		break;
 	}
@@ -452,8 +566,25 @@ int board_eth_init(bd_t *bis)
 			case 3:
 				mdio_mux[i] = EMI1_SLOT3;
 				fm_info_set_mdio(i, mii_dev_for_muxval(
-						mdio_mux[i]));
+						 mdio_mux[i]));
+				break;
+#if defined(CONFIG_T2081QDS)
+			case 5:
+				mdio_mux[i] = EMI1_SLOT5;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 6:
+				mdio_mux[i] = EMI1_SLOT6;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 7:
+				mdio_mux[i] = EMI1_SLOT7;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
 				break;
+#endif
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t208xqds/law.c
index 74e2a53..74e2a53 100644
--- a/board/freescale/t2080qds/law.c
+++ b/board/freescale/t208xqds/law.c
diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t208xqds/pci.c
index 84a89da..84a89da 100644
--- a/board/freescale/t2080qds/pci.c
+++ b/board/freescale/t208xqds/pci.c
diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
index c2ad0fd..c2ad0fd 100644
--- a/board/freescale/t2080qds/t2080_rcw.cfg
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_rcw.cfg
new file mode 100644
index 0000000..a2d5ecf
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
index e200d92..e200d92 100644
--- a/board/freescale/t2080qds/t2080_pbi.cfg
+++ b/board/freescale/t208xqds/t208x_pbi.cfg
diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t208xqds/t208xqds.c
index 4fe8ccb..9cfc0bd 100644
--- a/board/freescale/t2080qds/t2080qds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -20,8 +20,8 @@
 
 #include "../common/qixis.h"
 #include "../common/vsc3316_3308.h"
-#include "t2080qds.h"
-#include "t2080qds_qixis.h"
+#include "t208xqds.h"
+#include "t208xqds_qixis.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -89,19 +89,22 @@ int select_i2c_ch_pca9547(u8 ch)
 int brd_mux_lane_to_slot(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s1, srds_prtcl_s2;
+	u32 srds_prtcl_s1;
 
 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+#if defined(CONFIG_T2080QDS)
+	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+#endif
 
 	switch (srds_prtcl_s1) {
 	case 0:
 		/* SerDes1 is not enabled */
 		break;
+#if defined(CONFIG_T2080QDS)
 	case 0x1c:
 	case 0xa2:
 		/* SD1(A:D) => SLOT3 SGMII
@@ -180,12 +183,89 @@ int brd_mux_lane_to_slot(void)
 		 */
 		 QIXIS_WRITE(brdcfg[12], 0x1a);
 		 break;
+#elif defined(CONFIG_T2081QDS)
+	case 0x51:
+		/* SD1(A:D) => SLOT2 XAUI
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x98);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0x6b:
+		/* SD1(A:D) => XFI SFP Module
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x80);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0x6c:
+		/* SD1(A:B) => XFI SFP Module
+		 * SD1(C:D) => SLOT2 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xe8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0x6d:
+		/* SD1(A:B) => XFI SFP Module
+		 * SD1(C:D) => SLOT2 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xe8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0xaa:
+	case 0xab:
+		/* SD1(A:D) => SLOT2 PCIe3 x4
+		 * SD1(F:H) => SLOT1 SGMI4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xf8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0xca:
+	case 0xcb:
+		/* SD1(A)   => SLOT2 PCIe3 x1
+		 * SD1(B)   => SLOT7 SGMII
+		 * SD1(C)   => SLOT6 SGMII
+		 * SD1(D)   => SLOT5 SGMII
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x80);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0xde:
+	case 0xdf:
+		/* SD1(A:D) => SLOT2 PCIe3 x4
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F)   => SLOT4 PCIe1 x1
+		 * SD1(G)   => SLOT3 PCIe2 x1
+		 * SD1(H)   => SLOT7 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x98);
+		QIXIS_WRITE(brdcfg[13], 0x25);
+		break;
+	case 0xf2:
+		/* SD1(A)   => SLOT2 PCIe3 x1
+		 * SD1(B:D) => SLOT7 SGMII
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F)   => SLOT4 PCIe1 x1
+		 * SD1(G)   => SLOT3 PCIe2 x1
+		 * SD1(H)   => SLOT7 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x81);
+		QIXIS_WRITE(brdcfg[13], 0xa5);
+		break;
+#endif
 	default:
 		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 		       srds_prtcl_s1);
 		return -1;
 	}
 
+#ifdef CONFIG_T2080QDS
 	switch (srds_prtcl_s2) {
 	case 0:
 		/* SerDes2 is not enabled */
@@ -241,6 +321,7 @@ int brd_mux_lane_to_slot(void)
 		       srds_prtcl_s2);
 		return -1;
 	}
+#endif
 	return 0;
 }
 
diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t208xqds/t208xqds.h
index 39fcef2..39fcef2 100644
--- a/board/freescale/t2080qds/t2080qds.h
+++ b/board/freescale/t208xqds/t208xqds.h
diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
index fc83da7..bdcdc12 100644
--- a/board/freescale/t2080qds/t2080qds_qixis.h
+++ b/board/freescale/t208xqds/t208xqds_qixis.h
@@ -4,10 +4,10 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
-#ifndef __T2080QDS_QIXIS_H__
-#define __T2080QDS_QIXIS_H__
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
 
-/* Definitions of QIXIS Registers for T2080QDS */
+/* Definitions of QIXIS Registers for T208xQDS */
 
 #define QIXIS_SRDS1CLK_122		0x5a
 #define QIXIS_SRDS1CLK_125		0x5e
@@ -35,6 +35,8 @@
 
 #define BRDCFG5_IRE                     0x20    /* i2c Remote i2c1 enable */
 
+#define BRDCFG9_SFP_TX_EN		0x10
+
 #define BRDCFG12_SD3EN_MASK             0x20
 #define BRDCFG12_SD3MX_MASK             0x08
 #define BRDCFG12_SD3MX_SLOT5            0x08
diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t208xqds/tlb.c
index 62cd110..62cd110 100644
--- a/board/freescale/t2080qds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
diff --git a/board/h2200/Makefile b/board/h2200/Makefile
index d4fa153..e516e91 100644
--- a/board/h2200/Makefile
+++ b/board/h2200/Makefile
@@ -10,5 +10,5 @@ obj-y	:= h2200.o
 
 extra-y := h2200-header.bin
 
-$(obj)h2200-header.bin: $(obj)h2200-header.o
+$(obj)/h2200-header.bin: $(obj)/h2200-header.o
 	$(OBJCOPY) -O binary $< $@
diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h
index 703dbec..17c122c 100644
--- a/board/htkw/mcx/mcx.h
+++ b/board/htkw/mcx/mcx.h
@@ -325,8 +325,6 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | EN  | M4)) \
 	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(SYS_NRESWARM),	(IEN | PTU | DIS | M4)) \
-					/* SYS_nRESWARM */\
 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) \
 	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) \
 	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) \
diff --git a/board/hymod/config.mk b/board/hymod/config.mk
index abcd2d5..ee15890 100644
--- a/board/hymod/config.mk
+++ b/board/hymod/config.mk
@@ -11,4 +11,4 @@
 
 PLATFORM_CPPFLAGS += -I$(TOPDIR)
 
-OBJCFLAGS = --remove-section=.ppcenv
+OBJCOPYFLAGS = --remove-section=.ppcenv
diff --git a/board/ip04/config.mk b/board/ip04/config.mk
index ae2ea0b..bc0e747 100644
--- a/board/ip04/config.mk
+++ b/board/ip04/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 089a835..9f8fcf2 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -116,7 +116,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index cbfc7d2..51a3cfe 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -189,6 +189,31 @@ int wait_for_fpga_config(void)
 	return 0;
 }
 
+#if defined(KM_PCIE_RESET_MPP7)
+
+#define KM_PEX_RST_GPIO_PIN	7
+int fpga_reset(void)
+{
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	printf("PCIe reset through GPIO7: ");
+	/* apply PCIe reset via GPIO */
+	kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
+	kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
+	udelay(1000*10);
+	kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
+
+	printf(" done\n");
+
+	return 0;
+}
+
+#else
+
 #define PRST1		0x4
 #define PCIE_RST	0x10
 #define TRAFFIC_RST	0x04
@@ -219,6 +244,7 @@ int fpga_reset(void)
 
 	return 0;
 }
+#endif
 
 /* the FPGA was configured, we configure the BOCO2 so that the EEPROM
  * is available from the Bobcat SPI bus */
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 5620737..35402c8 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -46,7 +46,11 @@ static const u32 kwmpp_config[] = {
 	MPP4_NF_IO6,
 	MPP5_NF_IO7,
 	MPP6_SYSRST_OUTn,
+#if defined(KM_PCIE_RESET_MPP7)
+	MPP7_GPO,
+#else
 	MPP7_PEX_RST_OUTn,
+#endif
 #if defined(CONFIG_SYS_I2C_SOFT)
 	MPP8_GPIO,		/* SDA */
 	MPP9_GPIO,		/* SCL */
@@ -102,7 +106,7 @@ static const u32 kwmpp_config[] = {
 /*
  * Wait for startup OK from mgcoge3ne
  */
-int startup_allowed(void)
+static int startup_allowed(void)
 {
 	unsigned char buf;
 
@@ -164,7 +168,6 @@ static int initialize_unit_leds(void)
 	return 0;
 }
 
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
 static void set_bootcount_addr(void)
 {
 	uchar buf[32];
@@ -173,7 +176,6 @@ static void set_bootcount_addr(void)
 	sprintf((char *)buf, "0x%x", bootcountaddr);
 	setenv("bootcountaddr", (char *)buf);
 }
-#endif
 
 int misc_init_r(void)
 {
@@ -210,9 +212,7 @@ int misc_init_r(void)
 
 	initialize_unit_leds();
 	set_km_env();
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
 	set_bootcount_addr();
-#endif
 	return 0;
 }
 
@@ -322,15 +322,15 @@ void reset_phy(void)
 		return;
 
 	/* RGMII clk transition on data stable */
-	if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
+	if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
 		printf("Error reading PHY spec ctrl reg\n");
-	if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
-		reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
+	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+			 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
 		printf("Error writing PHY spec ctrl reg\n");
 
 	/* leds setup */
-	if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
-		PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
+	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+			 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
 		printf("Error writing PHY LED reg\n");
 
 	/* reset the phy */
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile
index 3e69ee2..c57ca08 100644
--- a/board/keymile/kmp204x/Makefile
+++ b/board/keymile/kmp204x/Makefile
@@ -8,5 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	:= kmp204x.o ddr.o eth.o tlb.o pci.o law.o \
+obj-y	:= kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \
 	../common/common.o ../common/ivm.o
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index f02642a..95a19cd 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -33,12 +33,51 @@ int checkboard(void)
 	return 0;
 }
 
-/* TODO: implement the I2C deblocking function */
-int i2c_make_abort(void)
+/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
+ * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
+ * For I2C only the low state is activly driven and high state is pulled-up
+ * by a resistor. Therefore the deblock GPIOs are used
+ *  -> as an active output to drive a low state
+ *  -> as an open-drain input to have a pulled-up high state
+ */
+
+/* QRIO GPIOs used for deblocking */
+#define DEBLOCK_PORT1	GPIO_A
+#define DEBLOCK_SCL1	20
+#define DEBLOCK_SDA1	21
+
+/* By default deblock GPIOs are floating */
+static void i2c_deblock_gpio_cfg(void)
+{
+	/* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
+	qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
+	qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
+
+	qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
+	qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
+}
+
+void set_sda(int state)
+{
+	qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
+}
+
+void set_scl(int state)
+{
+	qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
+}
+
+int get_sda(void)
+{
+	return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
+}
+
+int get_scl(void)
 {
-	return 1;
+	return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
 }
 
+
 #define ZL30158_RST	8
 #define ZL30343_RST	9
 
@@ -62,6 +101,7 @@ int board_early_init_f(void)
 
 int board_early_init_r(void)
 {
+	int ret = 0;
 	/* Flush d-cache and invalidate i-cache of any FLASH data */
 	flush_dcache();
 	invalidate_icache();
@@ -69,7 +109,11 @@ int board_early_init_r(void)
 	set_liodns();
 	setup_portals();
 
-	return 0;
+	ret = trigger_fpga_config();
+	if (ret)
+		printf("error triggering PCIe FPGA config\n");
+
+	return ret;
 }
 
 unsigned long get_board_sys_clk(unsigned long dummy)
@@ -77,80 +121,12 @@ unsigned long get_board_sys_clk(unsigned long dummy)
 	return 66666666;
 }
 
-#define WDMASK_OFF	0x16
-
-static void qrio_wdmask(u8 bit, bool wden)
-{
-	u16 wdmask;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
-	wdmask = in_be16(qrio_base + WDMASK_OFF);
-
-	if (wden)
-		wdmask |= (1 << bit);
-	else
-		wdmask &= ~(1 << bit);
-
-	out_be16(qrio_base + WDMASK_OFF, wdmask);
-}
-
-#define PRST_OFF	0x1a
-
-void qrio_prst(u8 bit, bool en, bool wden)
-{
-	u16 prst;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
-	qrio_wdmask(bit, wden);
-
-	prst = in_be16(qrio_base + PRST_OFF);
-
-	if (en)
-		prst &= ~(1 << bit);
-	else
-		prst |= (1 << bit);
-
-	out_be16(qrio_base + PRST_OFF, prst);
-}
-
-#define PRSTCFG_OFF	0x1c
-
-void qrio_prstcfg(u8 bit, u8 mode)
-{
-	u32 prstcfg;
-	u8 i;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
-	prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
-
-	for (i = 0; i < 2; i++) {
-		if (mode & (1<<i))
-			set_bit(2*bit+i, &prstcfg);
-		else
-			clear_bit(2*bit+i, &prstcfg);
-	}
-
-	out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
-}
-
-
-#define BOOTCOUNT_OFF	0x12
-
-void bootcount_store(ulong counter)
+int misc_init_f(void)
 {
-	u8 val;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
-	val = (counter <= 255) ? (u8)counter : 255;
-	out_8(qrio_base + BOOTCOUNT_OFF, val);
-}
+	/* configure QRIO pis for i2c deblocking */
+	i2c_deblock_gpio_cfg();
 
-ulong bootcount_load(void)
-{
-	u8 val;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-	val = in_8(qrio_base + BOOTCOUNT_OFF);
-	return val;
+	return 0;
 }
 
 #define NUM_SRDS_BANKS	2
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
index b6ba672..0267596 100644
--- a/board/keymile/kmp204x/kmp204x.h
+++ b/board/keymile/kmp204x/kmp204x.h
@@ -5,6 +5,16 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+/* QRIO GPIO ports */
+#define GPIO_A			0x40
+#define GPIO_B			0x60
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr);
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr);
+
 #define PRSTCFG_POWUP_UNIT_CORE_RST	0x0
 #define PRSTCFG_POWUP_UNIT_RST		0x1
 #define PRSTCFG_POWUP_RST		0x3
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg
index f38dcf9..9af8bd5 100644
--- a/board/keymile/kmp204x/pbi.cfg
+++ b/board/keymile/kmp204x/pbi.cfg
@@ -8,6 +8,16 @@
 #
 
 #PBI commands
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+#Freescale's errarta sheet suggests it may be done with PBI
+09000010 00000000
+09000014 00000000
+09000018 81d00000
+09021008 0000f000
+09021028 0000f000
+09021048 0000f000
+09021068 0000f000
+09000018 00000000
 #Initialize CPC1 as 1MB SRAM
 09010000 00200400
 09138000 00000000
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
index ec20c8a..a484eb5 100644
--- a/board/keymile/kmp204x/pci.c
+++ b/board/keymile/kmp204x/pci.c
@@ -14,18 +14,103 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
+#include <asm/errno.h>
 
 #include "kmp204x.h"
 
+#define PROM_SEL_L	11
+/* control the PROM_SEL_L signal*/
+static void toggle_fpga_eeprom_bus(bool cpu_own)
+{
+	qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own);
+}
+
+#define CONF_SEL_L	10
+#define FPGA_PROG_L	19
+#define FPGA_DONE	18
+#define FPGA_INIT_L	17
+
+int trigger_fpga_config(void)
+{
+	int ret = 0, init_l;
+	/* approx 10ms */
+	u32 timeout = 10000;
+
+	/* make sure the FPGA_can access the EEPROM */
+	toggle_fpga_eeprom_bus(false);
+
+	/* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
+	qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0);
+
+	/* trigger the config start */
+	qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0);
+
+	/* small delay for INIT_L line */
+	udelay(10);
+
+	/* wait for FPGA_INIT to be asserted */
+	do {
+		init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L);
+		if (timeout-- == 0) {
+			printf("FPGA_INIT timeout\n");
+			ret = -EFAULT;
+			break;
+		}
+		udelay(10);
+	} while (init_l);
+
+	/* deassert FPGA_PROG, config should start */
+	qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1);
+
+	return ret;
+}
+
+/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
+static int wait_for_fpga_config(void)
+{
+	int ret = 0, done;
+	/* approx 5 s */
+	u32 timeout = 500000;
+
+	printf("PCIe FPGA config:");
+	do {
+		done = qrio_get_gpio(GPIO_A, FPGA_DONE);
+		if (timeout-- == 0) {
+			printf(" FPGA_DONE timeout\n");
+			ret = -EFAULT;
+			goto err_out;
+		}
+		udelay(10);
+	} while (!done);
+
+	printf(" done\n");
+
+err_out:
+	/* deactive CONF_SEL and give the CPU conf EEPROM access */
+	qrio_set_gpio(GPIO_A, CONF_SEL_L, 1);
+	toggle_fpga_eeprom_bus(true);
+
+	return ret;
+}
+
 #define PCIE_SW_RST	14
+#define PEXHC_SW_RST	13
 #define HOOPER_SW_RST	12
 
 void pci_init_board(void)
 {
+	/* first wait for the PCIe FPGA to be configured
+	 * it has been triggered earlier in board_early_init_r */
+	int ret = wait_for_fpga_config();
+	if (ret)
+		printf("error finishing PCIe FPGA config\n");
+
 	qrio_prst(PCIE_SW_RST, false, false);
+	qrio_prst(PEXHC_SW_RST, false, false);
 	qrio_prst(HOOPER_SW_RST, false, false);
 	/* Hooper is not direcly PCIe capable */
 	mdelay(50);
+
 	fsl_pcie_init_board(0);
 }
 
diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c
new file mode 100644
index 0000000..49f9aa2
--- /dev/null
+++ b/board/keymile/kmp204x/qrio.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "../common/common.h"
+#include "kmp204x.h"
+
+/* QRIO GPIO register offsets */
+#define DIRECT_OFF		0x18
+#define GPRT_OFF		0x1c
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr)
+{
+	u32 gprt;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+
+	return (gprt >> gpio_nr) & 1U;
+}
+
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
+{
+	u32 gprt, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+	if (value)
+		gprt |= mask;
+	else
+		gprt &= ~mask;
+
+	out_be32(qrio_base + port_off + GPRT_OFF, gprt);
+}
+
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	direct |= mask;
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+
+	qrio_set_gpio(port_off, gpio_nr, value);
+}
+
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	direct &= ~mask;
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	if (val == 0)
+		/* set to output -> GPIO drives low */
+		direct |= mask;
+	else
+		/* set to input -> GPIO floating */
+		direct &= ~mask;
+
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+#define WDMASK_OFF	0x16
+
+static void qrio_wdmask(u8 bit, bool wden)
+{
+	u16 wdmask;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	wdmask = in_be16(qrio_base + WDMASK_OFF);
+
+	if (wden)
+		wdmask |= (1 << bit);
+	else
+		wdmask &= ~(1 << bit);
+
+	out_be16(qrio_base + WDMASK_OFF, wdmask);
+}
+
+#define PRST_OFF	0x1a
+
+void qrio_prst(u8 bit, bool en, bool wden)
+{
+	u16 prst;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	qrio_wdmask(bit, wden);
+
+	prst = in_be16(qrio_base + PRST_OFF);
+
+	if (en)
+		prst &= ~(1 << bit);
+	else
+		prst |= (1 << bit);
+
+	out_be16(qrio_base + PRST_OFF, prst);
+}
+
+#define PRSTCFG_OFF	0x1c
+
+void qrio_prstcfg(u8 bit, u8 mode)
+{
+	u32 prstcfg;
+	u8 i;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
+
+	for (i = 0; i < 2; i++) {
+		if (mode & (1<<i))
+			set_bit(2*bit+i, &prstcfg);
+		else
+			clear_bit(2*bit+i, &prstcfg);
+	}
+
+	out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
+}
diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg
index f2b7fe3..2d4c48c 100644
--- a/board/keymile/kmp204x/rcw_kmp204x.cfg
+++ b/board/keymile/kmp204x/rcw_kmp204x.cfg
@@ -7,5 +7,5 @@ aa55aa55 010e0100
 #64 bytes RCW data
 14600000 00000000 28200000 00000000
 148E70CF CFC02000 58000000 41000000
-00000000 00000000 00000000 F4428002
+00000000 00000000 00000000 F0428002
 00000000 00000000 00000000 00000000
diff --git a/board/keymile/scripts/develop-arm.txt b/board/keymile/scripts/develop-arm.txt
index 922afea..d3c974f 100644
--- a/board/keymile/scripts/develop-arm.txt
+++ b/board/keymile/scripts/develop-arm.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=true
diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt
index a6bb1b1..a80812a 100644
--- a/board/keymile/scripts/develop-common.txt
+++ b/board/keymile/scripts/develop-common.txt
@@ -3,6 +3,7 @@ bootcmd=run ${subbootcmds}
 configure=run set_uimage; km_setboardid && saveenv && reset
 subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
 nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
 tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
 toolchain=/opt/eldk
 rootfssize=0
diff --git a/board/keymile/scripts/develop-ppc_82xx.txt b/board/keymile/scripts/develop-ppc_82xx.txt
index 909f6a3c..d3c974f 100644
--- a/board/keymile/scripts/develop-ppc_82xx.txt
+++ b/board/keymile/scripts/develop-ppc_82xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/develop-ppc_8xx.txt b/board/keymile/scripts/develop-ppc_8xx.txt
index 909f6a3c..d3c974f 100644
--- a/board/keymile/scripts/develop-ppc_8xx.txt
+++ b/board/keymile/scripts/develop-ppc_8xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/ramfs-arm.txt b/board/keymile/scripts/ramfs-arm.txt
index 79974f1..87e984e 100644
--- a/board/keymile/scripts/ramfs-arm.txt
+++ b/board/keymile/scripts/ramfs-arm.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=true
diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt
index 502c863..d79ad2e 100644
--- a/board/keymile/scripts/ramfs-common.txt
+++ b/board/keymile/scripts/ramfs-common.txt
@@ -7,6 +7,7 @@ nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
 configure=run set_uimage; km_setboardid && saveenv && reset
 rootfsfile=${hostname}/rootfsImage
 setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
 tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
 tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage
 set_uimage=printenv uimage || setenv uimage uImage
diff --git a/board/keymile/scripts/ramfs-ppc_82xx.txt b/board/keymile/scripts/ramfs-ppc_82xx.txt
index 970927a..87e984e 100644
--- a/board/keymile/scripts/ramfs-ppc_82xx.txt
+++ b/board/keymile/scripts/ramfs-ppc_82xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/ramfs-ppc_8xx.txt b/board/keymile/scripts/ramfs-ppc_8xx.txt
index 970927a..87e984e 100644
--- a/board/keymile/scripts/ramfs-ppc_8xx.txt
+++ b/board/keymile/scripts/ramfs-ppc_8xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile
index 879d794..1bc1d61 100644
--- a/board/matrix_vision/mvblm7/Makefile
+++ b/board/matrix_vision/mvblm7/Makefile
@@ -8,5 +8,5 @@ obj-y	:= mvblm7.o pci.o fpga.o
 
 extra-y := bootscript.img
 
-$(obj)bootscript.img:
-	@mkimage -T script -C none -n M7_script -d bootscript $@
+$(obj)/bootscript.img: $(src)/bootscript
+	@mkimage -T script -C none -n M7_script -d $< $@
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
index c6c0933..c056eba 100644
--- a/board/matrix_vision/mvblx/Makefile
+++ b/board/matrix_vision/mvblx/Makefile
@@ -8,4 +8,4 @@
 obj-y += mvblx.o fpga.o
 obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
 
-CFLAGS += -Werror
+ccflags-y += -Werror
diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile
index b6a4f67..9454259 100644
--- a/board/matrix_vision/mvsmr/Makefile
+++ b/board/matrix_vision/mvsmr/Makefile
@@ -12,5 +12,5 @@ obj-y	:= mvsmr.o fpga.o
 
 extra-y := bootscript.img
 
-$(obj)bootscript.img: bootscript
+$(obj)/bootscript.img: $(src)/bootscript
 	@mkimage -T script -C none -n mvSMR_Script -d $< $@
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
index b889cf9..cca9c0c 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -197,13 +197,10 @@
 #define REFCNT_266		0
 /**************************************/
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 .globl lowlevel_init
 lowlevel_init:
 	/* use r0 to relocate DATA read/write to flash rather than memory ! */
-	ldr	r0, _TEXT_BASE
+	ldr	r0, =CONFIG_SYS_TEXT_BASE
 	ldr	r13, =BWSCON
 
 	/* enable minimal access to PLD */
diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h
index 4a230dd..0d2f0a5 100644
--- a/board/nokia/rx51/rx51.h
+++ b/board/nokia/rx51/rx51.h
@@ -22,8 +22,6 @@ struct emu_hal_params_rx51 {
 	u32 param4;
 };
 
-int print_cpuinfo(void);
-
 /*
  * IEN  - Input Enable
  * IDIS - Input Disable
diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile
index e3fcf2b..e3b2651 100644
--- a/board/nvidia/common/Makefile
+++ b/board/nvidia/common/Makefile
@@ -1,4 +1,4 @@
 # Copyright (c) 2011 The Chromium OS Authors.
 # SPDX-License-Identifier:	GPL-2.0+
 
-include common.mk
+include $(src)/common.mk
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index e650fed..3b18e28 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -67,12 +67,14 @@ void __gpio_early_init_uart(void)
 void gpio_early_init_uart(void)
 __attribute__((weak, alias("__gpio_early_init_uart")));
 
+#if defined(CONFIG_TEGRA_NAND)
 void __pin_mux_nand(void)
 {
 	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
 }
 
 void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
+#endif
 
 void __pin_mux_display(void)
 {
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
deleted file mode 100644
index 435c01e..0000000
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ /dev/null
@@ -1,71 +0,0 @@
-/dts-v1/;
-
-#include "tegra114.dtsi"
-
-/ {
-	model = "NVIDIA Dalmore";
-	compatible = "nvidia,dalmore", "nvidia,tegra114";
-
-	aliases {
-		i2c0 = "/i2c@7000d000";
-		i2c1 = "/i2c@7000c000";
-		i2c2 = "/i2c@7000c400";
-		i2c3 = "/i2c@7000c500";
-		i2c4 = "/i2c@7000c700";
-		sdhci0 = "/sdhci@78000600";
-		sdhci1 = "/sdhci@78000400";
-		usb0 = "/usb@7d008000";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x80000000>;
-	};
-
-	i2c@7000c000 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c400 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c500 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c700 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000d000 {
-		status = "okay";
-		clock-frequency = <400000>;
-	};
-
-	spi@7000da00 {
-		status = "okay";
-		spi-max-frequency = <25000000>;
-	};
-
-	sdhci@78000400 {
-		cd-gpios = <&gpio 170 1>; /* gpio PV2 */
-		bus-width = <4>;
-		status = "okay";
-	};
-
-	sdhci@78000600 {
-		bus-width = <8>;
-		status = "okay";
-	};
-
-	usb@7d008000 {
-		/* SPDIF_IN: USB_VBUS_EN1 */
-		nvidia,vbus-gpio = <&gpio 86 0>;
-		status = "okay";
-	};
-};
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
deleted file mode 100644
index b115f87..0000000
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ /dev/null
@@ -1,105 +0,0 @@
-/dts-v1/;
-
-#include "tegra20.dtsi"
-
-/ {
-	model = "NVIDIA Tegra20 Harmony evaluation board";
-	compatible = "nvidia,harmony", "nvidia,tegra20";
-
-	aliases {
-		usb0 = "/usb@c5008000";
-		usb1 = "/usb@c5004000";
-		sdhci0 = "/sdhci@c8000600";
-		sdhci1 = "/sdhci@c8000200";
-	};
-
-	memory {
-		reg = <0x00000000 0x40000000>;
-	};
-
-	host1x {
-		status = "okay";
-		dc@54200000 {
-			status = "okay";
-			rgb {
-				status = "okay";
-				nvidia,panel = <&lcd_panel>;
-			};
-		};
-	};
-
-	serial@70006300 {
-		clock-frequency = < 216000000 >;
-	};
-
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 23 0>;		/* PC7 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
-	};
-
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		status = "disabled";
-	};
-
-	usb@c5000000 {
-		status = "disabled";
-	};
-
-	usb@c5004000 {
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
-	};
-
-	sdhci@c8000200 {
-		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 155 0>; /* gpio PT3 */
-		bus-width = <4>;
-	};
-
-	sdhci@c8000600 {
-		status = "okay";
-		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
-		bus-width = <8>;
-	};
-
-	lcd_panel: panel {
-		clock = <42430000>;
-		xres = <1024>;
-		yres = <600>;
-		left-margin = <138>;
-		right-margin = <34>;
-		hsync-len = <136>;
-		lower-margin = <4>;
-		upper-margin = <21>;
-		vsync-len = <4>;
-		hsync-active-high;
-		vsyncx-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 0 0>;
-		nvidia,backlight-enable-gpios = <&gpio 13 0>;	/* PB5 */
-		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
-		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
-		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
-		nvidia,panel-timings = <0 0 200 0 0>;
-	};
-};
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
deleted file mode 100644
index c0e2e1e..0000000
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ /dev/null
@@ -1,191 +0,0 @@
-/dts-v1/;
-
-#include "tegra20.dtsi"
-
-/ {
-	model = "NVIDIA Seaboard";
-	compatible = "nvidia,seaboard", "nvidia,tegra20";
-
-	chosen {
-		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
-	};
-
-	aliases {
-		/* This defines the order of our ports */
-		usb0 = "/usb@c5008000";
-		usb1 = "/usb@c5000000";
-		i2c0 = "/i2c@7000d000";
-		i2c1 = "/i2c@7000c000";
-		i2c2 = "/i2c@7000c400";
-		i2c3 = "/i2c@7000c500";
-		sdhci0 = "/sdhci@c8000600";
-		sdhci1 = "/sdhci@c8000400";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = < 0x00000000 0x40000000 >;
-	};
-
-	host1x {
-		status = "okay";
-		dc@54200000 {
-			status = "okay";
-			rgb {
-				status = "okay";
-				nvidia,panel = <&lcd_panel>;
-			};
-		};
-	};
-
-	/* This is not used in U-Boot, but is expected to be in kernel .dts */
-	i2c@7000d000 {
-		clock-frequency = <100000>;
-		pmic@34 {
-			compatible = "ti,tps6586x";
-			reg = <0x34>;
-
-			clk_32k: clock {
-				compatible = "fixed-clock";
-				/*
-				 * leave out for now due to CPP:
-				 * #clock-cells = <0>;
-				 */
-				clock-frequency = <32768>;
-			};
-		};
-	};
-
-	serial@70006300 {
-		clock-frequency = < 216000000 >;
-	};
-
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
-	};
-
-	i2c@7000c000 {
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		clock-frequency = <100000>;
-	};
-
-	kbc@7000e200 {
-		linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
-			0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
-			0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
-			0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
-			0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
-			0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
-			0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
-			0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
-			0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
-			0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
-			0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
-			0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
-			0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
-			0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
-			0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
-			0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
-			0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
-			0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
-			0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
-			0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
-			0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
-			0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
-			0x1f04008a>;
-		linux,fn-keymap = <0x05040002>;
-	};
-
-	emc@7000f400 {
-		emc-table@190000 {
-			reg = < 190000 >;
-			compatible = "nvidia,tegra20-emc-table";
-			clock-frequency = < 190000 >;
-			nvidia,emc-registers = < 0x0000000c 0x00000026
-				0x00000009 0x00000003 0x00000004 0x00000004
-				0x00000002 0x0000000c 0x00000003 0x00000003
-				0x00000002 0x00000001 0x00000004 0x00000005
-				0x00000004 0x00000009 0x0000000d 0x0000059f
-				0x00000000 0x00000003 0x00000003 0x00000003
-				0x00000003 0x00000001 0x0000000b 0x000000c8
-				0x00000003 0x00000007 0x00000004 0x0000000f
-				0x00000002 0x00000000 0x00000000 0x00000002
-				0x00000000 0x00000000 0x00000083 0xa06204ae
-				0x007dc010 0x00000000 0x00000000 0x00000000
-				0x00000000 0x00000000 0x00000000 0x00000000 >;
-		};
-		emc-table@380000 {
-			reg = < 380000 >;
-			compatible = "nvidia,tegra20-emc-table";
-			clock-frequency = < 380000 >;
-			nvidia,emc-registers = < 0x00000017 0x0000004b
-				0x00000012 0x00000006 0x00000004 0x00000005
-				0x00000003 0x0000000c 0x00000006 0x00000006
-				0x00000003 0x00000001 0x00000004 0x00000005
-				0x00000004 0x00000009 0x0000000d 0x00000b5f
-				0x00000000 0x00000003 0x00000003 0x00000006
-				0x00000006 0x00000001 0x00000011 0x000000c8
-				0x00000003 0x0000000e 0x00000007 0x0000000f
-				0x00000002 0x00000000 0x00000000 0x00000002
-				0x00000000 0x00000000 0x00000083 0xe044048b
-				0x007d8010 0x00000000 0x00000000 0x00000000
-				0x00000000 0x00000000 0x00000000 0x00000000 >;
-		};
-	};
-
-	usb@c5000000 {
-		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
-		dr_mode = "otg";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
-	};
-
-	sdhci@c8000400 {
-		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
-		bus-width = <4>;
-	};
-
-	sdhci@c8000600 {
-		status = "okay";
-		bus-width = <8>;
-	};
-
-	lcd_panel: panel {
-		/* Seaboard has 1366x768 */
-		clock = <70600000>;
-		xres = <1366>;
-		yres = <768>;
-		left-margin = <58>;
-		right-margin = <58>;
-		hsync-len = <58>;
-		lower-margin = <4>;
-		upper-margin = <4>;
-		vsync-len = <4>;
-		hsync-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 2 0>;
-		nvidia,backlight-enable-gpios = <&gpio 28 0>;	/* PD4 */
-		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
-		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
-		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
-		nvidia,panel-timings = <400 4 203 17 15>;
-	};
-};
diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts
deleted file mode 100644
index 1a526ba..0000000
--- a/board/nvidia/dts/tegra20-ventana.dts
+++ /dev/null
@@ -1,91 +0,0 @@
-/dts-v1/;
-
-#include "tegra20.dtsi"
-
-/ {
-	model = "NVIDIA Tegra20 Ventana evaluation board";
-	compatible = "nvidia,ventana", "nvidia,tegra20";
-
-	aliases {
-		usb0 = "/usb@c5008000";
-		sdhci0 = "/sdhci@c8000600";
-		sdhci1 = "/sdhci@c8000400";
-	};
-
-	memory {
-		reg = <0x00000000 0x40000000>;
-	};
-
-	host1x {
-		status = "okay";
-		dc@54200000 {
-			status = "okay";
-			rgb {
-				status = "okay";
-				nvidia,panel = <&lcd_panel>;
-			};
-		};
-	};
-
-	serial@70006300 {
-		clock-frequency = < 216000000 >;
-	};
-
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		status = "disabled";
-	};
-
-	usb@c5000000 {
-		status = "disabled";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
-	};
-
-	sdhci@c8000400 {
-		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
-		bus-width = <4>;
-	};
-
-	sdhci@c8000600 {
-		status = "okay";
-		bus-width = <8>;
-	};
-
-	lcd_panel: panel {
-		clock = <72072000>;
-		xres = <1366>;
-		yres = <768>;
-		left-margin = <58>;
-		right-margin = <58>;
-		hsync-len = <58>;
-		lower-margin = <4>;
-		upper-margin = <4>;
-		vsync-len = <4>;
-		hsync-active-high;
-		vsync-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 2 0>;
-		nvidia,backlight-enable-gpios = <&gpio 28 0>;	/* PD4 */
-		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
-		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
-		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
-		nvidia,panel-timings = <0 0 200 0 0>;
-	};
-};
diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts
deleted file mode 100644
index eb92264..0000000
--- a/board/nvidia/dts/tegra20-whistler.dts
+++ /dev/null
@@ -1,73 +0,0 @@
-/dts-v1/;
-
-#include "tegra20.dtsi"
-
-/ {
-	model = "NVIDIA Tegra20 Whistler evaluation board";
-	compatible = "nvidia,whistler", "nvidia,tegra20";
-
-	aliases {
-		i2c0 = "/i2c@7000d000";
-		usb0 = "/usb@c5008000";
-		sdhci0 = "/sdhci@c8000600";
-		sdhci1 = "/sdhci@c8000400";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = < 0x00000000 0x20000000 >;
-	};
-
-	serial@70006000 {
-		clock-frequency = < 216000000 >;
-	};
-
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		clock-frequency = <100000>;
-
-		pmic@3c {
-			compatible = "maxim,max8907b";
-			reg = <0x3c>;
-
-			clk_32k: clock {
-				compatible = "fixed-clock";
-				/*
-				 * leave out for now due to CPP:
-				 * #clock-cells = <0>;
-				 */
-				clock-frequency = <32768>;
-			};
-		};
-	};
-
-	usb@c5000000 {
-		status = "disabled";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
-	};
-
-	sdhci@c8000400 {
-		status = "okay";
-		wp-gpios = <&gpio 173 0>; /* gpio PV5 */
-		bus-width = <8>;
-	};
-
-	sdhci@c8000600 {
-		status = "okay";
-		bus-width = <8>;
-	};
-};
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
deleted file mode 100644
index a7cc93e..0000000
--- a/board/nvidia/dts/tegra30-beaver.dts
+++ /dev/null
@@ -1,77 +0,0 @@
-/dts-v1/;
-
-#include "tegra30.dtsi"
-
-/ {
-	model = "NVIDIA Beaver";
-	compatible = "nvidia,beaver", "nvidia,tegra30";
-
-	aliases {
-		i2c0 = "/i2c@7000d000";
-		i2c1 = "/i2c@7000c000";
-		i2c2 = "/i2c@7000c400";
-		i2c3 = "/i2c@7000c500";
-		i2c4 = "/i2c@7000c700";
-		sdhci0 = "/sdhci@78000600";
-		sdhci1 = "/sdhci@78000000";
-		usb0 = "/usb@7d008000";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x7ff00000>;
-	};
-
-	i2c@7000c000 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c400 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c500 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c700 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000d000 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	spi@7000da00 {
-		status = "okay";
-		spi-max-frequency = <25000000>;
-		spi-flash@1 {
-			compatible = "winbond,w25q32";
-			reg = <1>;
-			spi-max-frequency = <20000000>;
-		};
-	};
-
-	sdhci@78000000 {
-		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-		power-gpios = <&gpio 31 0>; /* gpio PD7 */
-		bus-width = <4>;
-	};
-
-	sdhci@78000600 {
-		status = "okay";
-		bus-width = <8>;
-	};
-
-	usb@7d008000 {
-		nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
-		status = "okay";
-	};
-};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
deleted file mode 100644
index ea2cf76..0000000
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ /dev/null
@@ -1,72 +0,0 @@
-/dts-v1/;
-
-#include "tegra30.dtsi"
-
-/ {
-	model = "NVIDIA Cardhu";
-	compatible = "nvidia,cardhu", "nvidia,tegra30";
-
-	aliases {
-		i2c0 = "/i2c@7000d000";
-		i2c1 = "/i2c@7000c000";
-		i2c2 = "/i2c@7000c400";
-		i2c3 = "/i2c@7000c500";
-		i2c4 = "/i2c@7000c700";
-		sdhci0 = "/sdhci@78000600";
-		sdhci1 = "/sdhci@78000000";
-		usb0 = "/usb@7d008000";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x40000000>;
-	};
-
-	i2c@7000c000 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c400 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c500 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000c700 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	i2c@7000d000 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
-
-	spi@7000da00 {
-		status = "okay";
-		spi-max-frequency = <25000000>;
-	};
-
-	sdhci@78000000 {
-		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-		power-gpios = <&gpio 31 0>; /* gpio PD7 */
-		bus-width = <4>;
-	};
-
-	sdhci@78000600 {
-		status = "okay";
-		bus-width = <8>;
-	};
-
-	usb@7d008000 {
-		nvidia,vbus-gpio = <&gpio 236 0>;	/* PDD4 */
-		status = "okay";
-	};
-};
diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/venice2/Makefile
new file mode 100644
index 0000000..5fac5ab
--- /dev/null
+++ b/board/nvidia/venice2/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= as3722_init.o
+obj-y	+= venice2.o
diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c
new file mode 100644
index 0000000..960fea7
--- /dev/null
+++ b/board/nvidia/venice2/as3722_init.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+	debug("%s entry\n", __func__);
+
+	/* Don't need to set up VDD_CORE - already done - by OTP */
+
+	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+	/*
+	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+	/*
+	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+	/*
+	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.2V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+}
diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h
new file mode 100644
index 0000000..2a9e7cd
--- /dev/null
+++ b/board/nvidia/venice2/as3722_init.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR		0x80
+
+#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
+#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
+#define AS3722_SDCONTROL_REG	0x4D
+
+#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC */
+#define AS3722_LDCONTROL_REG	0x4E
+
+#define AS3722_SD0VOLTAGE_DATA	(0x2800 | AS3722_SD0VOLTAGE_REG)
+#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES	0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
new file mode 100644
index 0000000..50868e6
--- /dev/null
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -0,0 +1,339 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_VENICE2_H_
+#define _PINMUX_CONFIG_VENICE2_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od)	\
+	{								\
+		.pingroup   = PINGRP_##_pingroup,			\
+		.func       = PMUX_FUNC_##_mux,				\
+		.pull       = PMUX_PULL_##_pull,			\
+		.tristate   = PMUX_TRI_##_tri,				\
+		.io         = PMUX_PIN_##_io,				\
+		.lock       = PMUX_PIN_LOCK_##_lock,			\
+		.od         = PMUX_PIN_OD_##_od,			\
+		.ioreset    = PMUX_PIN_IO_RESET_DEFAULT,		\
+	}
+
+#define USB_PINMUX CEC_PINMUX
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.padgrp = PDRIVE_PINGROUP_##_padgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PGRP_LPMD_##_lpmd,		\
+		.schmt  = PGRP_SCHMT_##_schmt,		\
+		.hsm    = PGRP_HSM_##_hsm,		\
+	}
+
+static struct pingroup_config tegra124_pinmux_common[] = {
+	/* EXTPERIPH1 pinmux */
+	DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2S0 pinmux */
+	DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2S1 pinmux */
+	DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2S3 pinmux */
+	DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLDVFS pinmux */
+	DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+	/* ULPI pinmux */
+	DEFAULT_PINMUX(ULPI_DATA0,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA1,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4,    ULPI,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5,    ULPI,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6,    ULPI,        NORMAL,    NORMAL,   INPUT),
+
+	/* EC KBC/SPI */
+	DEFAULT_PINMUX(ULPI_CLK,      SPI1,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DIR,      SPI1,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_NXT,      SPI1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_STP,      SPI1,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2C3 (TPM) pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* UARTD pinmux (UART4 on Servo board, unused) */
+	DEFAULT_PINMUX(GPIO_PJ7,      UARTD,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GPIO_PB0,      UARTD,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PB1,      UARTD,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PK7,      UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* SPI4 (Winbond 'boot ROM') */
+	DEFAULT_PINMUX(GPIO_PG5,       SPI4,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PG6,       SPI4,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PG7,       SPI4,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PI3,       SPI4,        NORMAL,    NORMAL,   INPUT),
+
+	/* Touch IRQ */
+	DEFAULT_PINMUX(GPIO_W3_AUD,   RSVD1,       NORMAL,    NORMAL,   INPUT),
+
+	/* PWM1 pinmux */
+	DEFAULT_PINMUX(GPIO_PH1,       PWM1,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      UP,        NORMAL,   INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_IN,  SDMMC3,  UP,        TRISTATE, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3,  DOWN,      NORMAL,   INPUT),
+
+	/* SDMMC4 pinmux */
+	DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      UP,        NORMAL,   INPUT),
+
+	/* BLINK pinmux */
+	DEFAULT_PINMUX(CLK_32K_OUT,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* KBC pinmux */
+	DEFAULT_PINMUX(KB_COL0,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL1,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL2,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW0,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW1,       KBC,         UP,        NORMAL,   INPUT),
+
+	/* Misc */
+	DEFAULT_PINMUX(GPIO_PV0,      RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(KB_ROW7,       RSVD1,       UP,        NORMAL,   INPUT),
+
+	/* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
+	DEFAULT_PINMUX(KB_ROW9,       UARTA,       UP,        NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(KB_ROW10,      UARTA,       UP,        TRISTATE, INPUT),
+
+	/* I2CPWR pinmux (I2C5) */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* RTCK pinmux */
+	DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLK pinmux */
+	DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    TRISTATE, INPUT),
+
+	/* PWRON pinmux */
+	DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CPU pinmux */
+	DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+	/* PMI pinmux */
+	DEFAULT_PINMUX(PWR_INT_N,     PMI,         NORMAL,    TRISTATE, INPUT),
+
+	/* RESET_OUT_N pinmux */
+	DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+	/* EXTPERIPH3 pinmux */
+	DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* UARTB, GPS */
+	DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(UART2_RXD,     UARTB,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART2_TXD,     UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* UARTC (WIFI/BT) */
+	DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,     UARTC,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CEC pinmux */
+	CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* I2C4 (HDMI_DDC) pinmux */
+	DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+	DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+
+	/* USB pinmux */
+	USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* Unused, marked SNN_ on schematic, TRISTATE 'em */
+	DEFAULT_PINMUX(GPIO_PBB0,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5,     RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC1,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC2,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PH3,      GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PI7,      GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PJ2,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_X5_AUD,   RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_X6_AUD,   GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_W2_AUD,   RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PFF2,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(USB_VBUS_EN2,  RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_COL5,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW2,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW3,       KBC,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW5,       RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW6,       KBC,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW13,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW14,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW16,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(OWR,           RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7,    ULPI,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_FS,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK,     RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CLK2_OUT,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(SDMMC1_WP_N,   RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CAM_MCLK,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CLK3_REQ,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(CLK1_REQ,      RSVD3,    DOWN, TRISTATE, OUTPUT),
+};
+
+/* Initially setting all used GPIO's to non-TRISTATE */
+static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
+	DEFAULT_PINMUX(GPIO_X4_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_X7_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_W2_AUD,     RSVD1,  UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_X3_AUD,     RSVD3,  UP,      NORMAL,    INPUT),
+
+	/* EN_VDD_BL */
+	DEFAULT_PINMUX(DAP3_DOUT,       I2S2,   DOWN,    NORMAL,    OUTPUT),
+
+	/* MODEM */
+	DEFAULT_PINMUX(GPIO_PV0,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PV1,        RSVD1,  NORMAL,  NORMAL,    INPUT),
+
+	/* BOOT_SEL0-3 */
+	DEFAULT_PINMUX(GPIO_PG0,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG1,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG2,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG3,         GMI,    NORMAL,  NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(CLK2_REQ,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+
+	DEFAULT_PINMUX(KB_COL3,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_COL4,		SDMMC3, UP,	 NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL6,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_COL7,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_ROW4,         KBC,    DOWN,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW8,         KBC,    UP,      NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(GPIO_PU4,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PU5,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(HDMI_INT,        RSVD1,  DOWN,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPDIF_IN,	USB,	NORMAL,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CD_N,     SDMMC3, UP,       NORMAL,   INPUT),
+
+	/* TS_SHDN_L */
+	DEFAULT_PINMUX(GPIO_PK1,        GMI,    NORMAL,   NORMAL,   OUTPUT),
+};
+
+static struct padctrl_config venice2_padctrl[] = {
+	/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+		       SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
+};
+#endif /* PINMUX_CONFIG_VENICE2_H */
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c
new file mode 100644
index 0000000..1ed2fd7
--- /dev/null
+++ b/board/nvidia/venice2/venice2.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-venice2.h"
+#include <i2c.h>
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra124_pinmux_set_nontristate,
+			    ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+
+	pinmux_config_table(tegra124_pinmux_common,
+			    ARRAY_SIZE(tegra124_pinmux_common));
+
+	pinmux_config_table(unused_pins_lowpower,
+			    ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
+}
diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk
index 1e76128..b90d5d0 100644
--- a/board/pcs440ep/config.mk
+++ b/board/pcs440ep/config.mk
@@ -10,7 +10,7 @@
 #
 
 # Check the U-Boot Image with a SHA1 checksum
-ALL-y += $(obj)u-boot.sha1
+ALL-y += u-boot.sha1
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
 
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 7e5e07f..1071662 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -176,13 +176,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RGMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RGMII,
 	},
 };
diff --git a/board/pr1/config.mk b/board/pr1/config.mk
index 5c18d5c..2436ec0 100644
--- a/board/pr1/config.mk
+++ b/board/pr1/config.mk
@@ -9,6 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index 22bd6b1..7d2bb8c 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -8,6 +8,7 @@
 obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
 obj-$(CONFIG_THOR_FUNCTION) += thor.o
 obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
+obj-$(CONFIG_MISC_COMMON) += misc.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_BOARD_COMMON)	+= board.o
diff --git a/board/samsung/common/dfu_sample_env.txt b/board/samsung/common/dfu_sample_env.txt
new file mode 100644
index 0000000..d6ee8a2
--- /dev/null
+++ b/board/samsung/common/dfu_sample_env.txt
@@ -0,0 +1,9 @@
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4
+loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage
+mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2
diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds
index 8e3b73e..b22f9e0 100644
--- a/board/samsung/common/exynos-uboot-spl.lds
+++ b/board/samsung/common/exynos-uboot-spl.lds
@@ -42,7 +42,11 @@ SECTIONS
 	. = ALIGN(4);
 
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
 
 	.bss :
 	{
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
new file mode 100644
index 0000000..eb15739
--- /dev/null
+++ b/board/samsung/common/misc.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <libtizen.h>
+#include <samsung/misc.h>
+#include <errno.h>
+#include <version.h>
+#include <asm/sizes.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <linux/input.h>
+#include <power/pmic.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void)
+{
+	char info[64];
+
+	snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f,
+		 (s5p_cpu_rev & 0xf0) >> 0x04);
+	setenv("soc_rev", info);
+
+	snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);
+	setenv("soc_id", info);
+
+#ifdef CONFIG_REVISION_TAG
+	snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev());
+	setenv("board_rev", info);
+#endif
+#ifdef CONFIG_OF_LIBFDT
+	snprintf(info, ARRAY_SIZE(info),  "%s%x-%s.dtb",
+		 CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD);
+	setenv("fdtfile", info);
+#endif
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
+
+#ifdef CONFIG_LCD_MENU
+static int power_key_pressed(u32 reg)
+{
+	struct pmic *pmic;
+	u32 status;
+	u32 mask;
+
+	pmic = pmic_get(KEY_PWR_PMIC_NAME);
+	if (!pmic) {
+		printf("%s: Not found\n", KEY_PWR_PMIC_NAME);
+		return 0;
+	}
+
+	if (pmic_probe(pmic))
+		return 0;
+
+	if (reg == KEY_PWR_STATUS_REG)
+		mask = KEY_PWR_STATUS_MASK;
+	else
+		mask = KEY_PWR_INTERRUPT_MASK;
+
+	if (pmic_reg_read(pmic, reg, &status))
+		return 0;
+
+	return !!(status & mask);
+}
+
+static int key_pressed(int key)
+{
+	int value;
+
+	switch (key) {
+	case KEY_POWER:
+		value = power_key_pressed(KEY_PWR_INTERRUPT_REG);
+		break;
+	case KEY_VOLUMEUP:
+		value = !gpio_get_value(KEY_VOL_UP_GPIO);
+		break;
+	case KEY_VOLUMEDOWN:
+		value = !gpio_get_value(KEY_VOL_DOWN_GPIO);
+		break;
+	default:
+		value = 0;
+		break;
+	}
+
+	return value;
+}
+
+static int check_keys(void)
+{
+	int keys = 0;
+
+	if (key_pressed(KEY_POWER))
+		keys += KEY_POWER;
+	if (key_pressed(KEY_VOLUMEUP))
+		keys += KEY_VOLUMEUP;
+	if (key_pressed(KEY_VOLUMEDOWN))
+		keys += KEY_VOLUMEDOWN;
+
+	return keys;
+}
+
+/*
+ * 0 BOOT_MODE_INFO
+ * 1 BOOT_MODE_THOR
+ * 2 BOOT_MODE_UMS
+ * 3 BOOT_MODE_DFU
+ * 4 BOOT_MODE_EXIT
+ */
+static char *
+mode_name[BOOT_MODE_EXIT + 1] = {
+	"DEVICE",
+	"THOR",
+	"UMS",
+	"DFU",
+	"EXIT"
+};
+
+static char *
+mode_info[BOOT_MODE_EXIT + 1] = {
+	"info",
+	"downloader",
+	"mass storage",
+	"firmware update",
+	"and run normal boot"
+};
+
+#define MODE_CMD_ARGC	4
+
+static char *
+mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = {
+	{"", "", "", ""},
+	{"thor", "0", "mmc", "0"},
+	{"ums", "0", "mmc", "0"},
+	{"dfu", "0", "mmc", "0"},
+	{"", "", "", ""},
+};
+
+static void display_board_info(void)
+{
+#ifdef CONFIG_GENERIC_MMC
+	struct mmc *mmc = find_mmc_device(0);
+#endif
+	vidinfo_t *vid = &panel_info;
+
+	lcd_position_cursor(4, 4);
+
+	lcd_printf("%s\n\t", U_BOOT_VERSION);
+	lcd_puts("\n\t\tBoard Info:\n");
+#ifdef CONFIG_SYS_BOARD
+	lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	lcd_printf("\tBoard rev: %u\n", get_board_rev());
+#endif
+	lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS);
+	lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M);
+
+#ifdef CONFIG_GENERIC_MMC
+	if (mmc) {
+		if (!mmc->capacity)
+			mmc_init(mmc);
+
+		lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M);
+	}
+#endif
+	if (vid)
+		lcd_printf("\tDisplay resolution: %u x % u\n",
+			   vid->vl_col, vid->vl_row);
+
+	lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
+}
+
+static int mode_leave_menu(int mode)
+{
+	char *exit_option;
+	char *exit_boot = "boot";
+	char *exit_back = "back";
+	cmd_tbl_t *cmd;
+	int cmd_result;
+	int cmd_repeatable;
+	int leave;
+
+	lcd_clear();
+
+	switch (mode) {
+	case BOOT_MODE_EXIT:
+		return 1;
+	case BOOT_MODE_INFO:
+		display_board_info();
+		exit_option = exit_back;
+		leave = 0;
+		break;
+	default:
+		cmd = find_cmd(mode_cmd[mode][0]);
+		if (cmd) {
+			printf("Enter: %s %s\n", mode_name[mode],
+						 mode_info[mode]);
+			lcd_printf("\n\n\t%s %s\n", mode_name[mode],
+						    mode_info[mode]);
+			lcd_puts("\n\tDo not turn off device before finish!\n");
+
+			cmd_result = cmd_process(0, MODE_CMD_ARGC,
+						 *(mode_cmd + mode),
+						 &cmd_repeatable, NULL);
+
+			if (cmd_result == CMD_RET_SUCCESS) {
+				printf("Command finished\n");
+				lcd_clear();
+				lcd_printf("\n\n\t%s finished\n",
+					   mode_name[mode]);
+
+				exit_option = exit_boot;
+				leave = 1;
+			} else {
+				printf("Command error\n");
+				lcd_clear();
+				lcd_printf("\n\n\t%s command error\n",
+					   mode_name[mode]);
+
+				exit_option = exit_back;
+				leave = 0;
+			}
+		} else {
+			lcd_puts("\n\n\tThis mode is not supported.\n");
+			exit_option = exit_back;
+			leave = 0;
+		}
+	}
+
+	lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option);
+
+	/* Clear PWR button Rising edge interrupt status flag */
+	power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+	/* Wait for PWR key */
+	while (!key_pressed(KEY_POWER))
+		mdelay(1);
+
+	lcd_clear();
+	return leave;
+}
+
+static void display_download_menu(int mode)
+{
+	char *selection[BOOT_MODE_EXIT + 1];
+	int i;
+
+	for (i = 0; i <= BOOT_MODE_EXIT; i++)
+		selection[i] = "[  ]";
+
+	selection[mode] = "[=>]";
+
+	lcd_clear();
+	lcd_printf("\n\t\tDownload Mode Menu\n");
+
+	for (i = 0; i <= BOOT_MODE_EXIT; i++)
+		lcd_printf("\t%s  %s - %s\n\n", selection[i],
+						mode_name[i],
+						mode_info[i]);
+}
+
+static void download_menu(void)
+{
+	int mode = 0;
+	int last_mode = 0;
+	int run;
+	int key;
+
+	display_download_menu(mode);
+
+	while (1) {
+		run = 0;
+
+		if (mode != last_mode)
+			display_download_menu(mode);
+
+		last_mode = mode;
+		mdelay(100);
+
+		key = check_keys();
+		switch (key) {
+		case KEY_POWER:
+			run = 1;
+			break;
+		case KEY_VOLUMEUP:
+			if (mode > 0)
+				mode--;
+			break;
+		case KEY_VOLUMEDOWN:
+			if (mode < BOOT_MODE_EXIT)
+				mode++;
+			break;
+		default:
+			break;
+		}
+
+		if (run) {
+			if (mode_leave_menu(mode))
+				break;
+
+			display_download_menu(mode);
+		}
+	}
+
+	lcd_clear();
+}
+
+static void display_mode_info(void)
+{
+	lcd_position_cursor(4, 4);
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_puts("\nDownload Mode Menu\n");
+#ifdef CONFIG_SYS_BOARD
+	lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD);
+#endif
+	lcd_printf("Press POWER KEY to display MENU options.");
+}
+
+static int boot_menu(void)
+{
+	int key = 0;
+	int timeout = 10;
+
+	display_mode_info();
+
+	while (timeout--) {
+		lcd_printf("\rNormal boot will start in: %d seconds.", timeout);
+		mdelay(1000);
+
+		key = key_pressed(KEY_POWER);
+		if (key)
+			break;
+	}
+
+	lcd_clear();
+
+	/* If PWR pressed - show download menu */
+	if (key) {
+		printf("Power pressed - go to download menu\n");
+		download_menu();
+		printf("Download mode exit.\n");
+	}
+
+	return 0;
+}
+
+void check_boot_mode(void)
+{
+	int pwr_key;
+
+	pwr_key = power_key_pressed(KEY_PWR_STATUS_REG);
+	if (!pwr_key)
+		return;
+
+	/* Clear PWR button Rising edge interrupt status flag */
+	power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+	if (key_pressed(KEY_VOLUMEUP))
+		boot_menu();
+	else if (key_pressed(KEY_VOLUMEDOWN))
+		mode_leave_menu(BOOT_MODE_THOR);
+}
+
+void keys_init(void)
+{
+	/* Set direction to input */
+	gpio_direction_input(KEY_VOL_UP_GPIO);
+	gpio_direction_input(KEY_VOL_DOWN_GPIO);
+}
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void)
+{
+	int x, y;
+	ulong addr;
+
+	addr = panel_info.logo_addr;
+	if (!addr) {
+		error("There is no logo data.");
+		return;
+	}
+
+	if (panel_info.vl_width >= panel_info.logo_width) {
+		x = ((panel_info.vl_width - panel_info.logo_width) >> 1);
+		x += panel_info.logo_x_offset; /* For X center align */
+	} else {
+		x = 0;
+		printf("Warning: image width is bigger than display width\n");
+	}
+
+	if (panel_info.vl_height >= panel_info.logo_height) {
+		y = ((panel_info.vl_height - panel_info.logo_height) >> 1);
+		y += panel_info.logo_y_offset; /* For Y center align */
+	} else {
+		y = 0;
+		printf("Warning: image height is bigger than display height\n");
+	}
+
+	bmp_display(addr, x, y);
+}
+#endif /* CONFIG_CMD_BMP */
diff --git a/board/samsung/dts/exynos5250-arndale.dts b/board/samsung/dts/exynos5250-arndale.dts
deleted file mode 100644
index 202f2ea..0000000
--- a/board/samsung/dts/exynos5250-arndale.dts
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * SAMSUNG Arndale board device tree source
- *
- * Copyright (c) 2013 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-/dts-v1/;
-#include "exynos5250.dtsi"
-
-/ {
-	model = "SAMSUNG Arndale board based on EXYNOS5250";
-	compatible = "samsung,arndale", "samsung,exynos5250";
-
-	aliases {
-		serial0 = "/serial@12C20000";
-		console = "/serial@12C20000";
-	};
-
-	mmc@12200000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <1 3 3>;
-	};
-
-	mmc@12210000 {
-		status = "disabled";
-	};
-
-	mmc@12220000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-	};
-
-	mmc@12230000 {
-		status = "disabled";
-	};
-};
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts
deleted file mode 100644
index c4ed346..0000000
--- a/board/samsung/dts/exynos5250-smdk5250.dts
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * SAMSUNG SMDK5250 board device tree source
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/dts-v1/;
-/include/ "exynos5250.dtsi"
-
-/ {
-	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
-	compatible = "samsung,smdk5250", "samsung,exynos5250";
-
-	aliases {
-		i2c0 = "/i2c@12c60000";
-		i2c1 = "/i2c@12c70000";
-		i2c2 = "/i2c@12c80000";
-		i2c3 = "/i2c@12c90000";
-		i2c4 = "/i2c@12ca0000";
-		i2c5 = "/i2c@12cb0000";
-		i2c6 = "/i2c@12cc0000";
-		i2c7 = "/i2c@12cd0000";
-		spi0 = "/spi@12d20000";
-		spi1 = "/spi@12d30000";
-		spi2 = "/spi@12d40000";
-		spi3 = "/spi@131a0000";
-		spi4 = "/spi@131b0000";
-		mmc0 = "/mmc@12200000";
-		mmc1 = "/mmc@12210000";
-		mmc2 = "/mmc@12220000";
-		mmc3 = "/mmc@12230000";
-		serial0 = "/serial@12C30000";
-		console = "/serial@12C30000";
-		i2s = "/sound@3830000";
-	};
-
-	sromc@12250000 {
-		bank = <1>;
-		srom-timing = <1 9 12 1 6 1 1>;
-		width = <2>;
-		lan@5000000 {
-			compatible = "smsc,lan9215", "smsc,lan";
-			reg = <0x5000000 0x100>;
-			phy-mode = "mii";
-		};
-	};
-
-	sound@3830000 {
-		samsung,codec-type = "wm8994";
-	};
-
-	sound@12d60000 {
-		status = "disabled";
-	};
-
-	i2c@12c70000 {
-		soundcodec@1a {
-			reg = <0x1a>;
-			compatible = "wolfson,wm8994-codec";
-		};
-	};
-
-	i2c@12c60000 {
-		pmic@9 {
-			reg = <0x9>;
-			compatible = "maxim,max77686_pmic";
-		};
-	};
-
-	tmu@10060000 {
-		samsung,min-temp	= <25>;
-		samsung,max-temp	= <125>;
-		samsung,start-warning	= <95>;
-		samsung,start-tripping	= <105>;
-		samsung,hw-tripping	= <110>;
-		samsung,efuse-min-value	= <40>;
-		samsung,efuse-value	= <55>;
-		samsung,efuse-max-value	= <100>;
-		samsung,slope		= <274761730>;
-		samsung,dc-value	= <25>;
-	};
-
-	fimd@14400000 {
-		samsung,vl-freq = <60>;
-		samsung,vl-col = <2560>;
-		samsung,vl-row = <1600>;
-		samsung,vl-width = <2560>;
-		samsung,vl-height = <1600>;
-
-		samsung,vl-clkp;
-		samsung,vl-dp;
-		samsung,vl-bpix = <4>;
-
-		samsung,vl-hspw = <32>;
-		samsung,vl-hbpd = <80>;
-		samsung,vl-hfpd = <48>;
-		samsung,vl-vspw = <6>;
-		samsung,vl-vbpd = <37>;
-		samsung,vl-vfpd = <3>;
-		samsung,vl-cmd-allow-len = <0xf>;
-
-		samsung,winid = <3>;
-		samsung,interface-mode = <1>;
-		samsung,dp-enabled = <1>;
-		samsung,dual-lcd-enabled = <0>;
-	};
-
-	dp@145b0000 {
-		samsung,lt-status = <0>;
-
-		samsung,master-mode = <0>;
-		samsung,bist-mode = <0>;
-		samsung,bist-pattern = <0>;
-		samsung,h-sync-polarity = <0>;
-		samsung,v-sync-polarity = <0>;
-		samsung,interlaced = <0>;
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-	};
-
-	mmc@12200000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <1 3 3>;
-		samsung,removable = <0>;
-	};
-
-	mmc@12210000 {
-		status = "disabled";
-	};
-
-	mmc@12220000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		samsung,removable = <1>;
-	};
-
-	mmc@12230000 {
-		status = "disabled";
-	};
-
-	ehci@12110000 {
-		samsung,vbus-gpio = <&gpio 0xbe 0>; /* X26 */
-	};
-};
diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts
deleted file mode 100644
index 091cdb9..0000000
--- a/board/samsung/dts/exynos5250-snow.dts
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * SAMSUNG Snow board device tree source
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/dts-v1/;
-/include/ "exynos5250.dtsi"
-
-/ {
-	model = "Google Snow";
-	compatible = "google,snow", "samsung,exynos5250";
-
-	aliases {
-		i2c0 = "/i2c@12c60000";
-		i2c1 = "/i2c@12c70000";
-		i2c2 = "/i2c@12c80000";
-		i2c3 = "/i2c@12c90000";
-		i2c4 = "/i2c@12ca0000";
-		i2c5 = "/i2c@12cb0000";
-		i2c6 = "/i2c@12cc0000";
-		i2c7 = "/i2c@12cd0000";
-		spi0 = "/spi@12d20000";
-		spi1 = "/spi@12d30000";
-		spi2 = "/spi@12d40000";
-		spi3 = "/spi@131a0000";
-		spi4 = "/spi@131b0000";
-		mmc0 = "/mmc@12200000";
-		mmc1 = "/mmc@12210000";
-		mmc2 = "/mmc@12220000";
-		mmc3 = "/mmc@12230000";
-		serial0 = "/serial@12C30000";
-		console = "/serial@12C30000";
-		i2s = "/sound@3830000";
-	};
-
-	i2c4: i2c@12ca0000 {
-		cros-ec@1e {
-			reg = <0x1e>;
-			compatible = "google,cros-ec";
-			i2c-max-frequency = <100000>;
-			ec-interrupt = <&gpio 782 1>;
-		};
-
-		power-regulator@48 {
-			compatible = "ti,tps65090";
-			reg = <0x48>;
-		};
-	};
-
-	spi@131b0000 {
-		spi-max-frequency = <1000000>;
-		spi-deactivate-delay = <100>;
-		cros-ec@0 {
-			reg = <0>;
-			compatible = "google,cros-ec";
-			spi-max-frequency = <5000000>;
-			ec-interrupt = <&gpio 782 1>;
-			optimise-flash-write;
-			status = "disabled";
-		};
-	};
-
-	sound@3830000 {
-		samsung,codec-type = "max98095";
-		codec-enable-gpio = <&gpio 0xb7 0>;
-	};
-
-	sound@12d60000 {
-		status = "disabled";
-	};
-
-	i2c@12cd0000 {
-		soundcodec@22 {
-			reg = <0x22>;
-			compatible = "maxim,max98095-codec";
-		};
-	};
-
-	i2c@12c60000 {
-		pmic@9 {
-			reg = <0x9>;
-			compatible = "maxim,max77686_pmic";
-		};
-	};
-
-	mmc@12200000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <1 3 3>;
-		samsung,removable = <0>;
-	};
-
-	mmc@12210000 {
-		status = "disabled";
-	};
-
-	mmc@12220000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		samsung,removable = <1>;
-	};
-
-	mmc@12230000 {
-		status = "disabled";
-	};
-
-	ehci@12110000 {
-		samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
-	};
-
-	xhci@12000000 {
-		samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
-	};
-
-	tmu@10060000 {
-		samsung,min-temp	= <25>;
-		samsung,max-temp	= <125>;
-		samsung,start-warning	= <95>;
-		samsung,start-tripping	= <105>;
-		samsung,hw-tripping	= <110>;
-		samsung,efuse-min-value	= <40>;
-		samsung,efuse-value	= <55>;
-		samsung,efuse-max-value	= <100>;
-		samsung,slope		= <274761730>;
-		samsung,dc-value	= <25>;
-	};
-
-	cros-ec-keyb {
-		compatible = "google,cros-ec-keyb";
-		google,key-rows = <8>;
-		google,key-columns = <13>;
-		google,repeat-delay-ms = <240>;
-		google,repeat-rate-ms = <30>;
-		google,ghost-filter;
-		/*
-		 * Keymap entries take the form of 0xRRCCKKKK where
-		 * RR=Row CC=Column KKKK=Key Code
-		 * The values below are for a US keyboard layout and
-		 * are taken from the Linux driver. Note that the
-		 * 102ND key is not used for US keyboards.
-		 */
-		linux,keymap = <
-			/* CAPSLCK F1         B          F10     */
-			0x0001003a 0x0002003b 0x00030030 0x00040044
-			/* N       =          R_ALT      ESC     */
-			0x00060031 0x0008000d 0x000a0064 0x01010001
-			/* F4      G          F7         H       */
-			0x0102003e 0x01030022 0x01040041 0x01060023
-			/* '       F9         BKSPACE    L_CTRL  */
-			0x01080028 0x01090043 0x010b000e 0x0200001d
-			/* TAB     F3         T          F6      */
-			0x0201000f 0x0202003d 0x02030014 0x02040040
-			/* ]       Y          102ND      [       */
-			0x0205001b 0x02060015 0x02070056 0x0208001a
-			/* F8      GRAVE      F2         5       */
-			0x02090042 0x03010029 0x0302003c 0x03030006
-			/* F5      6          -          \       */
-			0x0304003f 0x03060007 0x0308000c 0x030b002b
-			/* R_CTRL  A          D          F       */
-			0x04000061 0x0401001e 0x04020020 0x04030021
-			/* S       K          J          ;       */
-			0x0404001f 0x04050025 0x04060024 0x04080027
-			/* L       ENTER      Z          C       */
-			0x04090026 0x040b001c 0x0501002c 0x0502002e
-			/* V       X          ,          M       */
-			0x0503002f 0x0504002d 0x05050033 0x05060032
-			/* L_SHIFT /          .          SPACE   */
-			0x0507002a 0x05080035 0x05090034 0x050B0039
-			/* 1       3          4          2       */
-			0x06010002 0x06020004 0x06030005 0x06040003
-			/* 8       7          0          9       */
-			0x06050009 0x06060008 0x0608000b 0x0609000a
-			/* L_ALT   DOWN       RIGHT      Q       */
-			0x060a0038 0x060b006c 0x060c006a 0x07010010
-			/* E       R          W          I       */
-			0x07020012 0x07030013 0x07040011 0x07050017
-			/* U       R_SHIFT    P          O       */
-			0x07060016 0x07070036 0x07080019 0x07090018
-			/* UP      LEFT    */
-			0x070b0067 0x070c0069>;
-	};
-};
diff --git a/board/samsung/dts/exynos5420-smdk5420.dts b/board/samsung/dts/exynos5420-smdk5420.dts
deleted file mode 100644
index d739763..0000000
--- a/board/samsung/dts/exynos5420-smdk5420.dts
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * SAMSUNG SMDK5420 board device tree source
- *
- * Copyright (c) 2013 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "exynos5420.dtsi"
-
-/ {
-	model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
-	compatible = "samsung,smdk5420", "samsung,exynos5";
-
-	config {
-		hwid = "smdk5420 TEST A-A 9382";
-	};
-
-	aliases {
-		i2c0 = "/i2c@12c60000";
-		i2c1 = "/i2c@12c70000";
-		i2c2 = "/i2c@12c80000";
-		i2c3 = "/i2c@12c90000";
-		i2c4 = "/i2c@12ca0000";
-		i2c5 = "/i2c@12cb0000";
-		i2c6 = "/i2c@12cc0000";
-		i2c7 = "/i2c@12cd0000";
-		i2c8 = "/i2c@12e00000";
-		i2c9 = "/i2c@12e10000";
-		i2c10 = "/i2c@12e20000";
-		spi0 = "/spi@12d20000";
-		spi1 = "/spi@12d30000";
-		spi2 = "/spi@12d40000";
-		spi3 = "/spi@131a0000";
-		spi4 = "/spi@131b0000";
-		mmc0 = "/mmc@12200000";
-		mmc1 = "/mmc@12210000";
-		mmc2 = "/mmc@12220000";
-		xhci0 = "/xhci@12000000";
-		xhci1 = "/xhci@12400000";
-		serial0 = "/serial@12C30000";
-		console = "/serial@12C30000";
-	};
-
-	tmu@10060000 {
-		samsung,min-temp	= <25>;
-		samsung,max-temp	= <125>;
-		samsung,start-warning	= <95>;
-		samsung,start-tripping	= <105>;
-		samsung,hw-tripping	= <110>;
-		samsung,efuse-min-value	= <40>;
-		samsung,efuse-value	= <55>;
-		samsung,efuse-max-value	= <100>;
-		samsung,slope		= <274761730>;
-		samsung,dc-value	= <25>;
-	};
-
-	/* s2mps11 is on i2c bus 4 */
-	i2c@12ca0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pmic@66 {
-			reg = <0x66>;
-			compatible = "samsung,s2mps11-pmic";
-		};
-	};
-
-	spi@12d20000 { /* spi0 */
-		spi-max-frequency = <50000000>;
-		firmware_storage_spi: flash@0 {
-			reg = <0>;
-		};
-	};
-
-	fimd@14400000 {
-		samsung,vl-freq = <60>;
-		samsung,vl-col = <2560>;
-		samsung,vl-row = <1600>;
-		samsung,vl-width = <2560>;
-		samsung,vl-height = <1600>;
-
-		samsung,vl-clkp;
-		samsung,vl-dp;
-		samsung,vl-bpix = <4>;
-
-		samsung,vl-hspw = <32>;
-		samsung,vl-hbpd = <80>;
-		samsung,vl-hfpd = <48>;
-		samsung,vl-vspw = <6>;
-		samsung,vl-vbpd = <37>;
-		samsung,vl-vfpd = <3>;
-		samsung,vl-cmd-allow-len = <0xf>;
-
-		samsung,winid = <3>;
-		samsung,interface-mode = <1>;
-		samsung,dp-enabled = <1>;
-		samsung,dual-lcd-enabled = <0>;
-	};
-
-	sound@3830000 {
-		samsung,codec-type = "wm8994";
-	};
-
-	i2c@12c70000 {
-		soundcodec@1a {
-			reg = <0x1a>;
-			compatible = "wolfson,wm8994-codec";
-		};
-	};
-
-	mmc@12200000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <1 3 3>;
-		samsung,removable = <0>;
-		samsung,pre-init;
-	};
-
-	mmc@12210000 {
-		status = "disabled";
-	};
-
-	mmc@12220000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		samsung,removable = <1>;
-	};
-
-	mmc@12230000 {
-		status = "disabled";
-	};
-
-	fimd@14400000 {
-		/* sysmmu is not used in U-Boot */
-		samsung,disable-sysmmu;
-	};
-
-	dp@145b0000 {
-		samsung,lt-status = <0>;
-
-		samsung,master-mode = <0>;
-		samsung,bist-mode = <0>;
-		samsung,bist-pattern = <0>;
-		samsung,h-sync-polarity = <0>;
-		samsung,v-sync-polarity = <0>;
-		samsung,interlaced = <0>;
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-	};
-
-	dmc {
-		mem-type = "ddr3";
-	};
-
-	xhci1: xhci@12400000 {
-		compatible = "samsung,exynos5250-xhci";
-		reg = <0x12400000 0x10000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		phy {
-			compatible = "samsung,exynos5250-usb3-phy";
-			reg = <0x12500000 0x100>;
-		};
-	};
-};
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 366f648..61b9ece 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -13,10 +13,17 @@
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
 #include <power/max8998_pmic.h>
+#include <samsung/misc.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct s5pc110_gpio *s5pc110_gpio;
 
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
 int board_init(void)
 {
 	/* Set Initial global variables */
@@ -173,3 +180,13 @@ struct s3c_plat_otg_data s5pc110_otg_data = {
 	.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
 };
 #endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+	return 0;
+}
+#endif
diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S
index 726211a..d52bc09 100644
--- a/board/samsung/goni/lowlevel_init.S
+++ b/board/samsung/goni/lowlevel_init.S
@@ -22,9 +22,6 @@
  * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
  */
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 	.globl lowlevel_init
 lowlevel_init:
 	mov	r11, lr
diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile
index e8818bf..1add9fe 100644
--- a/board/samsung/origen/Makefile
+++ b/board/samsung/origen/Makefile
@@ -4,16 +4,19 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifndef CONFIG_SPL_BUILD
-obj-y	+= origen.o
-endif
-
 ifdef CONFIG_SPL_BUILD
-all: $(OBJTREE)/tools/mk$(BOARD)spl
-endif
+# necessary to create built-in.o
+obj- := __dummy__.o
 
-# Fix ME after we implement hostprogs-y.
-ifdef CONFIG_SPL_BUILD
-$(OBJTREE)/tools/mk$(BOARD)spl:	tools/mkv310_image.c
-	$(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+hostprogs-y := tools/mkorigenspl
+always := $(hostprogs-y)
+
+# omit -O2 option to suppress
+#   warning: dereferencing type-punned pointer will break strict-aliasing rules
+#
+# TODO:
+# Fix the root cause in tools/mkorigenspl.c and delete the following work-around
+$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+else
+obj-y	+= origen.o
 endif
diff --git a/board/samsung/origen/tools/mkv310_image.c b/board/samsung/origen/tools/mkorigenspl.c
index 3ed20ef..3ed20ef 100644
--- a/board/samsung/origen/tools/mkv310_image.c
+++ b/board/samsung/origen/tools/mkorigenspl.c
diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S
index c7b78fd..5de04f1 100644
--- a/board/samsung/smdk2410/lowlevel_init.S
+++ b/board/samsung/smdk2410/lowlevel_init.S
@@ -110,16 +110,13 @@
 #define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
 /**************************************/
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 .globl lowlevel_init
 lowlevel_init:
 	/* memory control configuration */
 	/* make r0 relative the current location so that it */
 	/* reads SMRDATA out of FLASH rather than memory ! */
 	ldr     r0, =SMRDATA
-	ldr	r1, _TEXT_BASE
+	ldr	r1, =CONFIG_SYS_TEXT_BASE
 	sub	r0, r0, r1
 	ldr	r1, =BWSCON	/* Bus Width Status Controller */
 	add     r2, r0, #13*4
diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S
deleted file mode 100644
index 9003e2d..0000000
--- a/board/samsung/smdk5250/lowlevel_init.S
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Lowlevel setup for SMDK5250 board based on S5PC520
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-	.globl lowlevel_init
-lowlevel_init:
-
-	/* use iRAM stack in bl2 */
-	ldr	sp, =CONFIG_IRAM_STACK
-	stmdb	r13!, {ip,lr}
-
-	/* check reset status */
-	ldr	r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
-	ldr	r1, [r0]
-
-	/* AFTR wakeup reset */
-	ldr	r2, =S5P_CHECK_DIDLE
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* LPA wakeup reset */
-	ldr	r2, =S5P_CHECK_LPA
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* Sleep wakeup reset */
-	ldr	r2, =S5P_CHECK_SLEEP
-	cmp	r1, r2
-	beq	wakeup_reset
-
-	/*
-	 * If U-boot is already running in RAM, no need to relocate U-Boot.
-	 * Memory controller must be configured before relocating U-Boot
-	 * in ram.
-	 */
-	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
-	bic	r1, pc, r0		/* pc <- current addr of code */
-					/* r1 <- unmasked bits of pc */
-	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
-	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
-	cmp	r1, r2			/* compare r1, r2 */
-	beq	1f			/* r0 == r1 then skip sdram init */
-
-	/* init system clock */
-	bl	system_clock_init
-
-	/* Memory initialize */
-	bl	mem_ctrl_init
-
-1:
-	bl	arch_cpu_init
-	bl	tzpc_init
-	ldmia	r13!, {ip,pc}
-
-wakeup_reset:
-	bl	system_clock_init
-	bl	mem_ctrl_init
-	bl	arch_cpu_init
-	bl	tzpc_init
-
-exit_wakeup:
-	/* Load return address and jump to kernel */
-	ldr	r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
-
-	/* r1 = physical address of exynos5_cpu_resume function*/
-	ldr	r1, [r0]
-
-	/* Jump to kernel */
-	mov	pc, r1
-	nop
-	nop
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 943c29a..a69f73d 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -26,22 +26,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_USB_EHCI_EXYNOS
-static int board_usb_vbus_init(void)
-{
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
-	/* Enable VBUS power switch */
-	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
-
-	/* VBUS turn ON time */
-	mdelay(3);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_SOUND_MAX98095
 static void  board_enable_audio_codec(void)
 {
@@ -56,9 +40,6 @@ static void  board_enable_audio_codec(void)
 
 int exynos_init(void)
 {
-#ifdef CONFIG_USB_EHCI_EXYNOS
-	board_usb_vbus_init();
-#endif
 #ifdef CONFIG_SOUND_MAX98095
 	board_enable_audio_codec();
 #endif
diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S
index 4df0974..65e6b7a 100644
--- a/board/samsung/smdkc100/lowlevel_init.S
+++ b/board/samsung/smdkc100/lowlevel_init.S
@@ -17,9 +17,6 @@
  * r5 has zero always
  */
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 	.globl lowlevel_init
 lowlevel_init:
 	mov	r9, lr
diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile
index dbc621b..de0da16 100644
--- a/board/samsung/smdkv310/Makefile
+++ b/board/samsung/smdkv310/Makefile
@@ -4,16 +4,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifndef CONFIG_SPL_BUILD
-obj-y	+= smdkv310.o
-endif
-
 ifdef CONFIG_SPL_BUILD
-all: $(OBJTREE)/tools/mk$(BOARD)spl
-endif
+# necessary to create built-in.o
+obj- := __dummy__.o
 
-# Fix ME after we implement hostprogs-y.
-ifdef CONFIG_SPL_BUILD
-$(OBJTREE)/tools/mk$(BOARD)spl:	tools/mkv310_image.c
-	$(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+hostprogs-y := tools/mksmdkv310spl
+always := $(hostprogs-y)
+else
+obj-y	+= smdkv310.o
 endif
diff --git a/board/samsung/smdkv310/tools/mkv310_image.c b/board/samsung/smdkv310/tools/mksmdkv310spl.c
index 9a64ca6..9a64ca6 100644
--- a/board/samsung/smdkv310/tools/mkv310_image.c
+++ b/board/samsung/smdkv310/tools/mksmdkv310spl.c
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 640a193..b725505 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -28,6 +28,7 @@
 #include <power/max17042_fg.h>
 #include <usb.h>
 #include <usb_mass_storage.h>
+#include <samsung/misc.h>
 
 #include "setup.h"
 
@@ -742,7 +743,7 @@ vidinfo_t panel_info = {
 	.vl_hsp		= CONFIG_SYS_LOW,
 	.vl_vsp		= CONFIG_SYS_LOW,
 	.vl_dp		= CONFIG_SYS_LOW,
-	.vl_bpix	= 5,	/* Bits per pixel, 2^5 = 32 */
+	.vl_bpix	= 4,	/* Bits per pixel, 2^4 = 16 */
 
 	/* s6e8ax0 Panel infomation */
 	.vl_hspw	= 5,
@@ -786,3 +787,21 @@ void init_panel_info(vidinfo_t *vid)
 
 	setenv("lcdinfo", "lcd=s6e8ax0");
 }
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+	keys_init();
+	check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+	if (panel_info.logo_on)
+		draw_logo();
+#endif
+	return 0;
+}
+#endif
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index be15357..c17c24d 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -28,6 +28,7 @@
 #include <usb.h>
 #include <usb/s3c_udc.h>
 #include <usb_mass_storage.h>
+#include <samsung/misc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -72,15 +73,12 @@ static void check_hw_revision(void)
 int checkboard(void)
 {
 	puts("Board:\tTRATS2\n");
+	printf("HW Revision:\t0x%04x\n", board_rev);
+
 	return 0;
 }
 #endif
 
-static void show_hw_revision(void)
-{
-	printf("HW Revision:\t0x%04x\n", board_rev);
-}
-
 u32 get_board_rev(void)
 {
 	return board_rev;
@@ -144,17 +142,17 @@ static void board_init_i2c(void)
 int get_soft_i2c_scl_pin(void)
 {
 	if (I2C_ADAP_HWNR)
-		return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
+		return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */
 	else
-		return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
+		return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */
 }
 
 int get_soft_i2c_sda_pin(void)
 {
 	if (I2C_ADAP_HWNR)
-		return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
+		return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */
 	else
-		return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
+		return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */
 }
 #endif
 
@@ -568,7 +566,7 @@ vidinfo_t panel_info = {
 	.vl_hsp		= CONFIG_SYS_LOW,
 	.vl_vsp		= CONFIG_SYS_LOW,
 	.vl_dp		= CONFIG_SYS_LOW,
-	.vl_bpix	= 5,	/* Bits per pixel, 2^5 = 32 */
+	.vl_bpix	= 4,	/* Bits per pixel, 2^4 = 16 */
 
 	/* s6e8ax0 Panel infomation */
 	.vl_hspw	= 5,
@@ -618,11 +616,17 @@ void init_panel_info(vidinfo_t *vid)
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
-	setenv("model", "GT-I8800");
-	setenv("board", "TRATS2");
-
-	show_hw_revision();
-
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+	keys_init();
+	check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+	if (panel_info.logo_on)
+		draw_logo();
+#endif
 	return 0;
 }
 #endif
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 3feef3f..96da7e0 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -22,6 +22,7 @@
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
 #include <power/max8998_pmic.h>
+#include <samsung/misc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -446,7 +447,7 @@ vidinfo_t panel_info = {
 	.vl_vsp		= CONFIG_SYS_HIGH,
 	.vl_dp		= CONFIG_SYS_HIGH,
 
-	.vl_bpix	= 5,	/* Bits per pixel */
+	.vl_bpix	= 4,	/* Bits per pixel */
 
 	/* LD9040 LCD Panel */
 	.vl_hspw	= 2,
@@ -511,3 +512,21 @@ int board_init(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+	keys_init();
+	check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+	if (panel_info.logo_on)
+		draw_logo();
+#endif
+	return 0;
+}
+#endif
diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile
index f890008..ce29b41 100644
--- a/board/sandburst/karef/Makefile
+++ b/board/sandburst/karef/Makefile
@@ -10,11 +10,7 @@
 #
 
 # TBS: add for debugging purposes
-BUILDUSER := $(shell whoami)
-FORCEBUILD := $(shell rm -f karef.o)
-
-CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
-# TBS: end debugging
+ccflags-y += -DBUILDUSER='"$(shell whoami)"'
 
 obj-y	= karef.o ../common/flash.o ../common/sb_common.o
 extra-y	+= init.o
diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile
index 37d91a5..2c1028b 100644
--- a/board/sandburst/metrobox/Makefile
+++ b/board/sandburst/metrobox/Makefile
@@ -9,11 +9,7 @@
 #
 
 # TBS: add for debugging purposes
-BUILDUSER := $(shell whoami)
-FORCEBUILD := $(shell rm -f metrobox.o)
-
-CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
-# TBS: end debugging
+ccflags-y += -DBUILDUSER='"$(shell whoami)"'
 
 obj-y	= metrobox.o ../common/flash.o ../common/sb_common.o
 extra-y	+= init.o
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index 6c316fa..2172379 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -198,7 +198,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_MII,
 	},
 };
@@ -232,6 +232,13 @@ int board_eth_init(bd_t *bis)
 
 	factoryset_setenv();
 
+	/* Reset SMSC LAN9303 switch for default configuration */
+	gpio_request(GPIO_LAN9303_NRST, "nRST");
+	gpio_direction_output(GPIO_LAN9303_NRST, 0);
+	/* assert active low reset for 200us */
+	udelay(200);
+	gpio_set_value(GPIO_LAN9303_NRST, 1);
+
 	/* Set rgmii mode and enable rmii clock to be sourced from chip */
 	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 
diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c
index 5c22999..f2314b5 100644
--- a/board/siemens/dxr2/mux.c
+++ b/board/siemens/dxr2/mux.c
@@ -221,6 +221,8 @@ static struct module_pin_mux gpios_pin_mux[] = {
 	{OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
 	{OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
 	{OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
+	/* nRST for SMSC LAN9303 switch - GPIO2_24 */
+	{OFFSET(lcd_pclk), MODE(7) },			/* LAN9303 nRST */
 	{-1},
 };
 
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index ef3d6cc..98083d5 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -181,13 +181,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 25ab54d..e0ada3f 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -143,13 +143,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile
new file mode 100644
index 0000000..c8b4f9a
--- /dev/null
+++ b/board/silica/pengwyn/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
new file mode 100644
index 0000000..ee88b6f
--- /dev/null
+++ b/board/silica/pengwyn/board.c
@@ -0,0 +1,207 @@
+/*
+ * board.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <phy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#if defined(CONFIG_SPL_BUILD)
+
+/* DDR3 RAM timings */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K128MJT187E_RD_DQS,
+	.datawdsratio0 = MT41K128MJT187E_WR_DQS,
+	.datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K128MJT187E_RATIO,
+	.cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+	.cmd1csratio = MT41K128MJT187E_RATIO,
+	.cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+	.cmd2csratio = MT41K128MJT187E_RATIO,
+	.cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K128MJT187E_EMIF_SDCFG,
+	.ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
+	.sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
+	.sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
+	.sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
+	.zq_config = MT41K128MJT187E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr_266 = {
+		266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_303 = {
+		303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_400 = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	/*
+	 * The pengwyn board uses the TPS650250 PMIC  without I2C
+	 * interface and will output the following fixed voltages:
+	 * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
+	 * VLDO1=1V8 (IO) VLDO2=1V8(IO)
+	 * Vcore=1V1 is fixed, generated by TPS62231
+	 */
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* 720MHz cpu, this might change on newer board revisions */
+	dpll_mpu_opp100.m = MPUPLL_M_720;
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	/* future configs can return other clock settings */
+	return &dpll_ddr_303;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+	config_ddr(303, &ddr3_ioregs, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif /* if CONFIG_SPL_BUILD */
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_MII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+		.phy_if		= PHY_INTERFACE_MODE_MII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			return n;
+	}
+
+	writel(MII_MODE_ENABLE, &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+	return n;
+}
+#endif /* if CONFIG_DRIVER_TI_CPSW */
diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h
new file mode 100644
index 0000000..05addf6
--- /dev/null
+++ b/board/silica/pengwyn/board.h
@@ -0,0 +1,15 @@
+/*
+ * board.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#endif
diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c
new file mode 100644
index 0000000..c8be440
--- /dev/null
+++ b/board/silica/pengwyn/mux.c
@@ -0,0 +1,98 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
+
+/* I2C pins C16(scl)/C17(sda) */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+					PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+					PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
+	{-1},
+};
+
+/* MMC0 pins */
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},  /* MMC0_CD */
+	{-1},
+};
+
+/* MII pins */
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+/* NAND pins */
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(uart0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+}
diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile
index 08dc09f..b0ba320 100644
--- a/board/spear/common/Makefile
+++ b/board/spear/common/Makefile
@@ -5,7 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
 obj-y	:= spr_misc.o
 obj-y	+= spr_lowlevel_init.o
 endif
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index e25aba2..6b6bd9f 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
 	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-				interface) >= 0)
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif
 	return ret;
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 70f9aa1..a4c6a8e 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
 	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-				interface) >= 0)
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif
 #if defined(CONFIG_MACB)
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index f6b1fdd..ab732a7 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
 	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-				interface) >= 0)
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif
 #if defined(CONFIG_MACB)
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index e996a0e..8472002 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis)
 #if defined(CONFIG_DW_AUTONEG)
 	interface = PHY_INTERFACE_MODE_GMII;
 #endif
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-				interface) >= 0)
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif
 	return ret;
diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
index f9053fe..18d3dd2 100644
--- a/board/spear/x600/Makefile
+++ b/board/spear/x600/Makefile
@@ -5,6 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
 obj-y	:= fpga.o x600.o
 endif
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
index 044d204..b8edfcd 100644
--- a/board/spear/x600/x600.c
+++ b/board/spear/x600/x600.c
@@ -67,31 +67,32 @@ void board_nand_init(void)
 		fsmc_nand_init(nand);
 }
 
-int designware_board_phy_init(struct eth_device *dev, int phy_addr,
-	int (*mii_write)(struct eth_device *, u8, u8, u16),
-	int dw_reset_phy(struct eth_device *))
+int board_phy_config(struct phy_device *phydev)
 {
 	/* Extended PHY control 1, select GMII */
-	mii_write(dev, phy_addr, 23, 0x0020);
+	phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
 
 	/* Software reset necessary after GMII mode selction */
-	dw_reset_phy(dev);
+	phy_reset(phydev);
 
 	/* Enable extended page register access */
-	mii_write(dev, phy_addr, 31, 0x0001);
+	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
 
 	/* 17e: Enhanced LED behavior, needs to be written twice */
-	mii_write(dev, phy_addr, 17, 0x09ff);
-	mii_write(dev, phy_addr, 17, 0x09ff);
+	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
 
 	/* 16e: Enhanced LED method select */
-	mii_write(dev, phy_addr, 16, 0xe0ea);
+	phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
 
 	/* Disable extended page register access */
-	mii_write(dev, phy_addr, 31, 0x0000);
+	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
 
 	/* Enable clock output pin */
-	mii_write(dev, phy_addr, 18, 0x0049);
+	phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
 
 	return 0;
 }
@@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis)
 {
 	int ret = 0;
 
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE,
 				  PHY_INTERFACE_MODE_GMII) >= 0)
 		ret++;
 
diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile
index 6867a70..f0605e2 100644
--- a/board/st-ericsson/snowball/Makefile
+++ b/board/st-ericsson/snowball/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS += -D__RELEASE -D__STN_8500
+ccflags-y += -D__RELEASE -D__STN_8500
 
 obj-y	:= snowball.o
diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile
index b9dfbe9..d6c4280 100644
--- a/board/st-ericsson/u8500/Makefile
+++ b/board/st-ericsson/u8500/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS += -D__RELEASE -D__STN_8500
+ccflags-y += -D__RELEASE -D__STN_8500
 
 obj-y	:= u8500_href.o gpio.o
diff --git a/board/synopsys/arcangel4/Makefile b/board/synopsys/arcangel4/Makefile
new file mode 100644
index 0000000..575e58f
--- /dev/null
+++ b/board/synopsys/arcangel4/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# This board is mostly used for debugging U-Boot in simulation (ISS).
+# The only peripheral which is used on this board is a serial port which
+# requires no initialization except those in "include/configs/arcangel4.h".
+# And now there's no specific initializations for this board.
+# So this Makefile is only required for satisfaction of U-Boot build system.
diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile
new file mode 100644
index 0000000..f0965f7
--- /dev/null
+++ b/board/synopsys/axs101/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= axs101.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
new file mode 100644
index 0000000..d1271ff
--- /dev/null
+++ b/board/synopsys/axs101/axs101.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_mmc_init(bd_t *bis)
+{
+	struct dwmci_host *host = NULL;
+
+	host = malloc(sizeof(struct dwmci_host));
+	if (!host) {
+		printf("dwmci_host malloc fail!\n");
+		return 1;
+	}
+
+	memset(host, 0, sizeof(struct dwmci_host));
+	host->name = "Synopsys Mobile storage";
+	host->ioaddr = (void *)ARC_DWMMC_BASE;
+	host->buswidth = 4;
+	host->dev_index = 0;
+	host->bus_hz = 25000000;
+
+	add_dwmci(host, 52000000, 400000);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	if (designware_initialize(ARC_DWGMAC_BASE,
+				  PHY_INTERFACE_MODE_RGMII) >= 0)
+		return 1;
+
+	return 0;
+}
diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c
new file mode 100644
index 0000000..8672803
--- /dev/null
+++ b/board/synopsys/axs101/nand.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <bouncebuf.h>
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/io.h>
+
+#define BUS_WIDTH	8		/* AXI data bus width in bytes	*/
+
+/* DMA buffer descriptor bits & masks */
+#define BD_STAT_OWN			(1 << 31)
+#define BD_STAT_BD_FIRST		(1 << 3)
+#define BD_STAT_BD_LAST			(1 << 2)
+#define BD_SIZES_BUFFER1_MASK		0xfff
+
+#define BD_STAT_BD_COMPLETE	(BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
+
+/* Controller command flags */
+#define B_WFR		(1 << 19)	/* 1b - Wait for ready		*/
+#define B_LC		(1 << 18)	/* 1b - Last cycle		*/
+#define B_IWC		(1 << 13)	/* 1b - Interrupt when complete	*/
+
+/* NAND cycle types */
+#define B_CT_ADDRESS	(0x0 << 16)	/* Address operation		*/
+#define B_CT_COMMAND	(0x1 << 16)	/* Command operation		*/
+#define B_CT_WRITE	(0x2 << 16)	/* Write operation		*/
+#define B_CT_READ	(0x3 << 16)	/* Write operation		*/
+
+enum nand_isr_t {
+	NAND_ISR_DATAREQUIRED = 0,
+	NAND_ISR_TXUNDERFLOW,
+	NAND_ISR_TXOVERFLOW,
+	NAND_ISR_DATAAVAILABLE,
+	NAND_ISR_RXUNDERFLOW,
+	NAND_ISR_RXOVERFLOW,
+	NAND_ISR_TXDMACOMPLETE,
+	NAND_ISR_RXDMACOMPLETE,
+	NAND_ISR_DESCRIPTORUNAVAILABLE,
+	NAND_ISR_CMDDONE,
+	NAND_ISR_CMDAVAILABLE,
+	NAND_ISR_CMDERROR,
+	NAND_ISR_DATATRANSFEROVER,
+	NAND_ISR_NONE
+};
+
+enum nand_regs_t {
+	AC_FIFO = 0,		/* address and command fifo */
+	IDMAC_BDADDR = 0x18,	/* idmac descriptor list base address */
+	INT_STATUS = 0x118,	/* interrupt status register */
+	INT_CLR_STATUS = 0x120,	/* interrupt clear status register */
+};
+
+struct nand_bd {
+	uint32_t status;	/* DES0 */
+	uint32_t sizes;		/* DES1 */
+	uint32_t buffer_ptr0;	/* DES2 */
+	uint32_t buffer_ptr1;	/* DES3 */
+};
+
+#define NAND_REG_WRITE(r, v)	writel(v, CONFIG_SYS_NAND_BASE + r)
+#define NAND_REG_READ(r)	readl(CONFIG_SYS_NAND_BASE + r)
+
+static struct nand_bd *bd;	/* DMA buffer descriptors	*/
+
+/**
+ * axs101_nand_write_buf -  write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static uint32_t nand_flag_is_set(uint32_t flag)
+{
+	uint32_t reg = NAND_REG_READ(INT_STATUS);
+
+	if (reg & (1 << NAND_ISR_CMDERROR))
+		return 0;
+
+	if (reg & (1 << flag)) {
+		NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * axs101_nand_write_buf -  write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
+				   int len)
+{
+	struct bounce_buffer bbstate;
+
+	bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
+
+	/* Setup buffer descriptor */
+	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+	writel(0, &bd->buffer_ptr1);
+
+	/* Issue "write" command */
+	NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
+
+	/* Wait for NAND command and DMA to complete */
+	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+		;
+	while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
+		;
+
+	bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_buf -  read chip data into buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer to store data
+ * @len:	number of bytes to read
+ */
+static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	struct bounce_buffer bbstate;
+
+	bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
+
+	/* Setup buffer descriptor */
+	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+	writel(0, &bd->buffer_ptr1);
+
+	/* Issue "read" command */
+	NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
+
+	/* Wait for NAND command and DMA to complete */
+	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+		;
+	while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
+		;
+
+	bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_byte -  read one byte from the chip
+ * @mtd:	MTD device structure
+ */
+static u_char axs101_nand_read_byte(struct mtd_info *mtd)
+{
+	u8 byte;
+
+	axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+	return byte;
+}
+
+/**
+ * axs101_nand_read_word -  read one word from the chip
+ * @mtd:	MTD device structure
+ */
+static u16 axs101_nand_read_word(struct mtd_info *mtd)
+{
+	u16 word;
+
+	axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+	return word;
+}
+
+/**
+ * axs101_nand_hwcontrol - NAND control functions wrapper.
+ * @mtd:	MTD device structure
+ * @cmd:	Command
+ */
+static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
+				   unsigned int ctrl)
+{
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	cmd = cmd & 0xff;
+
+	switch (ctrl & (NAND_ALE | NAND_CLE)) {
+	/* Address */
+	case NAND_ALE:
+		cmd |= B_CT_ADDRESS;
+		break;
+
+	/* Command */
+	case NAND_CLE:
+		cmd |= B_CT_COMMAND | B_WFR;
+
+		break;
+
+	default:
+		debug("%s: unknown ctrl %#x\n", __func__, ctrl);
+	}
+
+	NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
+	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+		;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
+					sizeof(struct nand_bd));
+
+	/* Set buffer descriptor address in IDMAC */
+	NAND_REG_WRITE(IDMAC_BDADDR, bd);
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = axs101_nand_hwcontrol;
+	nand->read_byte = axs101_nand_read_byte;
+	nand->read_word = axs101_nand_read_word;
+	nand->write_buf = axs101_nand_write_buf;
+	nand->read_buf = axs101_nand_read_buf;
+
+	return 0;
+}
diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk
index f1ef9bf..0d3df2d 100644
--- a/board/tcm-bf518/config.mk
+++ b/board/tcm-bf518/config.mk
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk
index 973d357..97eaafe 100644
--- a/board/tcm-bf537/config.mk
+++ b/board/tcm-bf537/config.mk
@@ -7,9 +7,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 5721768..7609a18 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -544,12 +544,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 	},
 };
 
@@ -602,6 +602,21 @@ int board_eth_init(bd_t *bis)
 	}
 
 #ifdef CONFIG_DRIVER_TI_CPSW
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
index 6a734b3..ceb2022 100644
--- a/board/ti/am335x/u-boot.lds
+++ b/board/ti/am335x/u-boot.lds
@@ -77,7 +77,12 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 	/*
 	 * Deprecated: this MMU section is used by pxa at present but
@@ -108,7 +113,7 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
-	.dynsym _end : { *(.dynsym) }
+	.dynsym _image_binary_end : { *(.dynsym) }
 	.dynbss : { *(.dynbss) }
 	.dynstr : { *(.dynstr*) }
 	.dynamic : { *(.dynamic*) }
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 4e6846a..d744977 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -19,9 +19,13 @@
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
+#include <miiphy.h>
+#include <cpsw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -200,7 +204,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x50074BE4,
 	.temp_alert_config		= 0x0,
-	.emif_ddr_phy_ctlr_1		= 0x0E084008,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
 	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
 	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
@@ -346,14 +350,14 @@ static void enable_vtt_regulator(void)
 	u32 temp;
 
 	/* enable module */
-	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
-
-	/* enable output for GPIO0_22 */
-	writel(GPIO_SETDATAOUT(GPIO_22),
-	       AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
-	temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
-	temp = temp & ~(GPIO_OE_ENABLE(GPIO_22));
-	writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
+	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
+
+	/* enable output for GPIO5_7 */
+	writel(GPIO_SETDATAOUT(7),
+	       AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
+	temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+	temp = temp & ~(GPIO_OE_ENABLE(7));
+	writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 }
 
 void sdram_init(void)
@@ -402,3 +406,97 @@ int board_late_init(void)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+	/* Additional controls can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 16,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("ethaddr")) {
+		puts("<ethaddr> not set. Validating first E-fuse MAC\n");
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
+	if (board_is_eposevm()) {
+		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+		cpsw_slaves[0].phy_addr = 16;
+	} else {
+		writel(RGMII_MODE_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+		cpsw_slaves[0].phy_addr = 0;
+	}
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+
+	return rv;
+}
+#endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 810b194..77c53d2 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -11,6 +11,41 @@
 #include <asm/arch/mux.h>
 #include "board.h"
 
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RD0 */
+	{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},	/* RMII1_RXDV */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_refclk */
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
 static struct module_pin_mux uart0_pin_mux[] = {
 	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
 	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
@@ -33,8 +68,18 @@ static struct module_pin_mux i2c0_pin_mux[] = {
 	{-1},
 };
 
-static struct module_pin_mux gpio0_22_pin_mux[] = {
-	{OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)},	/* GPIO0_22 */
+static struct module_pin_mux gpio5_7_pin_mux[] = {
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)},	/* GPIO5_7 */
+	{-1},
+};
+
+static struct module_pin_mux qspi_pin_mux[] = {
+	{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+	{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+	{OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+	{OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+	{OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+	{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
 	{-1},
 };
 
@@ -47,9 +92,15 @@ void enable_board_pin_mux(void)
 {
 	configure_module_pin_mux(mmc0_pin_mux);
 	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mdio_pin_mux);
 
-	if (board_is_gpevm())
-		configure_module_pin_mux(gpio0_22_pin_mux);
+	if (board_is_gpevm()) {
+		configure_module_pin_mux(gpio5_7_pin_mux);
+		configure_module_pin_mux(rgmii1_pin_mux);
+	} else if (board_is_eposevm()) {
+		configure_module_pin_mux(rmii1_pin_mux);
+		configure_module_pin_mux(qspi_pin_mux);
+	}
 }
 
 void enable_i2c0_pin_mux(void)
diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README
new file mode 100644
index 0000000..2fdaeac
--- /dev/null
+++ b/board/ti/dra7xx/README
@@ -0,0 +1,25 @@
+Summary
+=======
+
+This document covers various features of the 'dra7xx_evm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2.  In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} dra7xx/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 1b60b8f..c6c4fd1 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -12,6 +12,7 @@
  */
 #include <common.h>
 #include <palmas.h>
+#include <sata.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sata.h>
@@ -80,7 +81,7 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	omap_sata_init();
+	init_sata(0);
 	return 0;
 }
 
@@ -148,12 +149,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 2,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 3,
 	},
 };
 
@@ -215,6 +216,21 @@ int board_eth_init(bd_t *bis)
 		if (is_valid_ether_addr(mac_addr))
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
+
+	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = mac_hi & 0xFF;
+	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+	mac_addr[5] = mac_lo & 0xFF;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
 	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 	ctrl_val |= 0x22;
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S
index cad0a5a..e05a1c7 100644
--- a/board/ti/omap5912osk/lowlevel_init.S
+++ b/board/ti/omap5912osk/lowlevel_init.S
@@ -18,10 +18,6 @@
 #include <./configs/omap1510.h>
 #endif
 
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
 .globl lowlevel_init
 lowlevel_init:
 
diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README
new file mode 100644
index 0000000..970e2ec
--- /dev/null
+++ b/board/ti/omap5_uevm/README
@@ -0,0 +1,25 @@
+Summary
+=======
+
+This document covers various features of the 'omap5_uevm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2.  In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} omap5uevm/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index b549d72..3eaa5ac 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -15,6 +15,7 @@
 #include "mux_data.h"
 
 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+#include <sata.h>
 #include <usb.h>
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
@@ -70,7 +71,7 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	omap_sata_init();
+	init_sata(0);
 	return 0;
 }
 
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 140ad71..54b3dfb 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -132,12 +132,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x50,
 		.sliver_reg_ofs	= 0x700,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 	},
 	{
 		.slave_reg_ofs	= 0x90,
 		.sliver_reg_ofs	= 0x740,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 	},
 };
 
diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts
deleted file mode 100644
index c0e54af..0000000
--- a/board/toradex/dts/tegra20-colibri_t20_iris.dts
+++ /dev/null
@@ -1,45 +0,0 @@
-/dts-v1/;
-
-#include "tegra20.dtsi"
-
-/ {
-	model = "Toradex Colibri T20";
-	compatible = "toradex,t20", "nvidia,tegra20";
-
-	aliases {
-		usb0 = "/usb@c5008000";
-		usb1 = "/usb@c5000000";
-		usb2 = "/usb@c5004000";
-		sdhci0 = "/sdhci@c8000600";
-	};
-
-	usb@c5000000 {
-		dr_mode = "otg";
-	};
-
-	usb@c5004000 {
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */
-		nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */
-	};
-
-	usb@c5008000 {
-		nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */
-	};
-
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */
-		nvidia,width = <8>;
-		nvidia,timing = <15 100 25 80 25 10 15 10 100>;
-
-		nand@0 {
-			reg = <0>;
-			compatible = "nand-flash";
-		};
-	};
-
-	sdhci@c8000600 {
-		status = "okay";
-		cd-gpios = <&gpio 23 1>; /* gpio PC7 */
-		bus-width = <4>;
-	};
-};
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index b6fdde4..5dbf94e 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -54,7 +54,12 @@ SECTIONS
 
 	. = ALIGN(0x800);
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
@@ -63,7 +68,7 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	.dynsym _end : { *(.dynsym) }
+	.dynsym _image_binary_end : { *(.dynsym) }
 	.dynbss : { *(.dynbss) }
 	.dynstr : { *(.dynstr*) }
 	.dynamic : { *(.dynamic*) }
diff --git a/board/xilinx/dts/microblaze-generic.dts b/board/xilinx/dts/microblaze-generic.dts
deleted file mode 100644
index 2033309..0000000
--- a/board/xilinx/dts/microblaze-generic.dts
+++ /dev/null
@@ -1,7 +0,0 @@
-/dts-v1/;
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	aliases {
-	} ;
-} ;
diff --git a/board/xilinx/dts/zynq-microzed.dts b/board/xilinx/dts/zynq-microzed.dts
deleted file mode 100644
index 6da71c1..0000000
--- a/board/xilinx/dts/zynq-microzed.dts
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Xilinx MicroZED board DTS
- *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-#include "zynq-7000.dtsi"
-
-/ {
-	model = "Zynq MicroZED Board";
-	compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
-};
diff --git a/board/xilinx/dts/zynq-zc702.dts b/board/xilinx/dts/zynq-zc702.dts
deleted file mode 100644
index 667dc28..0000000
--- a/board/xilinx/dts/zynq-zc702.dts
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Xilinx ZC702 board DTS
- *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-#include "zynq-7000.dtsi"
-
-/ {
-	model = "Zynq ZC702 Board";
-	compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
-};
diff --git a/board/xilinx/dts/zynq-zc706.dts b/board/xilinx/dts/zynq-zc706.dts
deleted file mode 100644
index 526fc88..0000000
--- a/board/xilinx/dts/zynq-zc706.dts
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Xilinx ZC706 board DTS
- *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-#include "zynq-7000.dtsi"
-
-/ {
-	model = "Zynq ZC706 Board";
-	compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
-};
diff --git a/board/xilinx/dts/zynq-zc770-xm010.dts b/board/xilinx/dts/zynq-zc770-xm010.dts
deleted file mode 100644
index 8b542a1..0000000
--- a/board/xilinx/dts/zynq-zc770-xm010.dts
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Xilinx ZC770 XM010 board DTS
- *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-#include "zynq-7000.dtsi"
-
-/ {
-	model = "Zynq ZC770 XM010 Board";
-	compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
-};
diff --git a/board/xilinx/dts/zynq-zc770-xm012.dts b/board/xilinx/dts/zynq-zc770-xm012.dts
deleted file mode 100644
index 0379a07..0000000
--- a/board/xilinx/dts/zynq-zc770-xm012.dts
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Xilinx ZC770 XM012 board DTS
- *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-#include "zynq-7000.dtsi"
-
-/ {
-	model = "Zynq ZC770 XM012 Board";
-	compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
-};
diff --git a/board/xilinx/dts/zynq-zc770-xm013.dts b/board/xilinx/dts/zynq-zc770-xm013.dts
deleted file mode 100644
index a4f9e05..0000000
--- a/board/xilinx/dts/zynq-zc770-xm013.dts
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Xilinx ZC770 XM013 board DTS
- *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-#include "zynq-7000.dtsi"
-
-/ {
-	model = "Zynq ZC770 XM013 Board";
-	compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
-};
diff --git a/board/xilinx/dts/zynq-zed.dts b/board/xilinx/dts/zynq-zed.dts
deleted file mode 100644
index 91a5deb..0000000
--- a/board/xilinx/dts/zynq-zed.dts
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Xilinx ZED board DTS
- *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-#include "zynq-7000.dtsi"
-
-/ {
-	model = "Zynq ZED Board";
-	compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
-};
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 6301a8c..3f19a1c 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -6,3 +6,4 @@
 #
 
 obj-y	:= board.o
+obj-$(CONFIG_SPL_BUILD)	+= ps7_init.o
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index a5b9bde..82f2345 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -12,17 +12,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* Bootmode setting values */
-#define ZYNQ_BM_MASK		0x0F
-#define ZYNQ_BM_NOR		0x02
-#define ZYNQ_BM_SD		0x05
-#define ZYNQ_BM_JTAG		0x0
-
 #ifdef CONFIG_FPGA
 Xilinx_desc fpga;
 
 /* It can be done differently */
 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
@@ -40,6 +35,9 @@ int board_init(void)
 	case XILINX_ZYNQ_7010:
 		fpga = fpga010;
 		break;
+	case XILINX_ZYNQ_7015:
+		fpga = fpga015;
+		break;
 	case XILINX_ZYNQ_7020:
 		fpga = fpga020;
 		break;
@@ -55,8 +53,6 @@ int board_init(void)
 	}
 #endif
 
-	icache_enable();
-
 #ifdef CONFIG_FPGA
 	fpga_init();
 	fpga_add(fpga_xilinx, &fpga);
@@ -85,7 +81,6 @@ int board_late_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bis)
 {
 	u32 ret = 0;
@@ -119,7 +114,6 @@ int board_eth_init(bd_t *bis)
 #endif
 	return ret;
 }
-#endif
 
 #ifdef CONFIG_CMD_MMC
 int board_mmc_init(bd_t *bd)
diff --git a/board/xilinx/zynq/ps7_init.c b/board/xilinx/zynq/ps7_init.c
new file mode 100644
index 0000000..c47da09
--- /dev/null
+++ b/board/xilinx/zynq/ps7_init.c
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/spl.h>
+
+__weak void ps7_init(void)
+{
+	puts("Please copy ps7_init.c/h from hw project\n");
+}