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authorTom Rini <trini@ti.com>2013-02-12 14:59:23 -0500
committerTom Rini <trini@ti.com>2013-02-12 14:59:23 -0500
commit1634e969189ea428bc5fb9cf7d70bb314c98fc4f (patch)
treedaf2d84d2a0d150632795ba64ffb75c166909d89 /board
parent951c6baaf44c7fd4335b75fb92840d4e42c94927 (diff)
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am335x_evm: Fix CPSW ethernet on GP EVM and EVM-SK
In commit cfd4ff6 we implemented part of advisory 1.0.10 (internal delay for RGMII mode not supported). This in turn however requires that we set the tx clock delay feature in the PHY itself. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board')
-rw-r--r--board/ti/am335x/board.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index b9ac1d5..48e6896 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -73,6 +73,11 @@ static inline int board_is_idk(void)
return !strncmp(header.config, "SKU#02", 6);
}
+static int board_is_gp_evm(void)
+{
+ return !strncmp("A33515BB", header.name, 8);
+}
+
int board_is_evm_15_or_later(void)
{
return (!strncmp("A33515BB", header.name, 8) &&
@@ -466,6 +471,28 @@ int board_eth_init(bd_t *bis)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
+
+ /*
+ *
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the AR8051 PHY. Since we only support a single ethernet
+ * device in U-Boot, we only do this for the first instance.
+ */
+#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8051_PHY_DEBUG_DATA_REG 0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
+#define AR8051_RGMII_TX_CLK_DLY 0x100
+
+ if (board_is_evm_sk() || board_is_gp_evm()) {
+ const char *devname;
+ devname = miiphy_get_current_dev();
+
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+ AR8051_DEBUG_RGMII_CLK_DLY_REG);
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+ AR8051_RGMII_TX_CLK_DLY);
+ }
#endif
try_usbether:
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)