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| author | Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> | 2020-10-23 04:58:58 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-10-27 08:13:33 +0100 |
| commit | 17a42abb40dd006b5f0e96d69e4894bef4c04ba8 (patch) | |
| tree | 5093c293bd04bc712e143d531e33834c3e12d005 /board | |
| parent | 7a49a16ec54e03ea6a383c1b97a78acc059c2df8 (diff) | |
| download | u-boot-17a42abb40dd006b5f0e96d69e4894bef4c04ba8.zip u-boot-17a42abb40dd006b5f0e96d69e4894bef4c04ba8.tar.gz u-boot-17a42abb40dd006b5f0e96d69e4894bef4c04ba8.tar.bz2 | |
mmc: Define timing macro's
Define timing macro's for all the available speeds of mmc. This is
done similar to linux. Replace speed macro's used with these new timing
macro's wherever applicable.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/xilinx/zynqmp/tap_delays.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c index 5fde0ae..1368370 100644 --- a/board/xilinx/zynqmp/tap_delays.c +++ b/board/xilinx/zynqmp/tap_delays.c @@ -8,6 +8,7 @@ #include <common.h> #include <asm/arch/sys_proto.h> #include <linux/delay.h> +#include <mmc.h> #define SD_DLL_CTRL 0xFF180358 #define SD_ITAP_DLY 0xFF180314 @@ -54,15 +55,6 @@ #define MMC_BANK2 0x2 -#define MMC_TIMING_UHS_SDR25 1 -#define MMC_TIMING_UHS_SDR50 2 -#define MMC_TIMING_UHS_SDR104 3 -#define MMC_TIMING_UHS_DDR50 4 -#define MMC_TIMING_MMC_HS200 5 -#define MMC_TIMING_SD_HS 6 -#define MMC_TIMING_MMC_DDR52 7 -#define MMC_TIMING_MMC_HS 8 - void zynqmp_dll_reset(u8 deviceid) { /* Issue DLL Reset */ |