Merge branch 'next'

Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>

63 files changed, 793 insertions, 1034 deletions

diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
index 5416a5b..0fd9532 100644
--- a/board/Arcturus/ucp1020/spl.c
+++ b/board/Arcturus/ucp1020/spl.c
@@ -83,8 +83,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c
index 2205dd3..a723ba7 100644
--- a/board/atmel/common/mac_eeprom.c
+++ b/board/atmel/common/mac_eeprom.c
@@ -36,3 +36,36 @@ int at91_set_ethaddr(int offset)
 
 	return 0;
 }
+
+/* this function will set eth1addr from a second eeprom, if available */
+int at91_set_eth1addr(int offset)
+{
+	const int ETH_ADDR_LEN = 6;
+	unsigned char ethaddr[ETH_ADDR_LEN];
+	/* configure eth1addr for second interface */
+	const char *ETHADDR_NAME = "eth1addr";
+	struct udevice *dev;
+	int ret;
+
+	if (env_get(ETHADDR_NAME))
+		return 0;
+
+	/* first eeprom is retrieved, this is for the first interface */
+	ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+	if (ret)
+		return ret;
+
+	/* attempt to obtain a second eeprom device */
+	ret = uclass_next_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = i2c_eeprom_read(dev, offset, ethaddr, 6);
+	if (ret)
+		return ret;
+
+	if (is_valid_ethaddr(ethaddr))
+		eth_env_set_enetaddr(ETHADDR_NAME, ethaddr);
+
+	return 0;
+}
diff --git a/board/broadcom/bcmns3/Kconfig b/board/broadcom/bcmns3/Kconfig
index 8ce21f9..cb73f98 100644
--- a/board/broadcom/bcmns3/Kconfig
+++ b/board/broadcom/bcmns3/Kconfig
@@ -12,4 +12,11 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "bcm_ns3"
 
+config CMD_BCM_EXT_UTILS
+	bool "Enable Broadcom-specific U-Boot commands"
+	default y
+	help
+	  Enable Broadcom specific U-Boot commands such as error log setup
+	  command or any other commands specific to NS3 platform.
+
 endif
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 0357cd0..10ae344 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -12,6 +12,7 @@
 #include <asm/armv8/mmu.h>
 #include <asm/arch-bcmns3/bl33_info.h>
 #include <dt-bindings/memory/bcm-ns3-mc.h>
+#include <broadcom/chimp.h>
 
 /* Default reset-level = 3 and strap-val = 0 */
 #define L3_RESET	30
@@ -210,8 +211,24 @@ void reset_cpu(ulong level)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *fdt, struct bd_info *bd)
 {
+	u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
+
 	gic_lpi_tables_init();
 
+	/*
+	 * Check for chimp handshake status.
+	 * Zero timeout value will actually fall to default timeout.
+	 *
+	 * System boot is independent of chimp handshake.
+	 * chimp handshake failure is not a catastrophic error.
+	 * Hence continue booting if chimp handshake fails.
+	 */
+	chimp_handshake_status_optee(0, &chimp_hs);
+	if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
+		printf("ChiMP handshake successful\n");
+	else
+		printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
+
 	return mem_info_parse_fixup(fdt);
 }
 #endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 4b49b6e..5811c43 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -49,11 +49,6 @@ int checkboard(void)
 	return 0;
 }
 
-int dram_init_banksize(void)
-{
-	return 0;
-}
-
 int board_postclk_init(void)
 {
 	/*
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index b0e109f..04e04a6 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -53,7 +53,6 @@ obj-$(CONFIG_TARGET_P1022DS)		+= ics307_clk.o
 obj-$(CONFIG_P2020DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P3041DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P4080DS)		+= ics307_clk.o
-obj-$(CONFIG_TARGET_P5020DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P5040DS)		+= ics307_clk.o
 obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
 obj-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o
diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
index 98b1add..e92b0d0 100644
--- a/board/freescale/corenet_ds/Kconfig
+++ b/board/freescale/corenet_ds/Kconfig
@@ -28,21 +28,6 @@ source "board/freescale/common/Kconfig"
 
 endif
 
-if TARGET_P5020DS
-
-config SYS_BOARD
-	default "corenet_ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "P5020DS"
-
-source "board/freescale/common/Kconfig"
-
-endif
-
 if TARGET_P5040DS
 
 config SYS_BOARD
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 708e812..e22cf70 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -6,22 +6,13 @@ F:	include/configs/P3041DS.h
 F:	configs/P3041DS_defconfig
 F:	configs/P3041DS_NAND_defconfig
 F:	configs/P3041DS_SDCARD_defconfig
-F:	configs/P3041DS_SECURE_BOOT_defconfig
 F:	configs/P3041DS_SPIFLASH_defconfig
 F:	configs/P3041DS_SRIO_PCIE_BOOT_defconfig
 F:	include/configs/P4080DS.h
 F:	configs/P4080DS_defconfig
 F:	configs/P4080DS_SDCARD_defconfig
-F:	configs/P4080DS_SECURE_BOOT_defconfig
 F:	configs/P4080DS_SPIFLASH_defconfig
 F:	configs/P4080DS_SRIO_PCIE_BOOT_defconfig
-F:	include/configs/P5020DS.h
-F:	configs/P5020DS_defconfig
-F:	configs/P5020DS_NAND_defconfig
-F:	configs/P5020DS_SDCARD_defconfig
-F:	configs/P5020DS_SECURE_BOOT_defconfig
-F:	configs/P5020DS_SPIFLASH_defconfig
-F:	configs/P5020DS_SRIO_PCIE_BOOT_defconfig
 F:	include/configs/P5040DS.h
 F:	configs/P5040DS_defconfig
 F:	configs/P5040DS_NAND_defconfig
@@ -33,5 +24,4 @@ CORENET_DS_SECURE_BOOT BOARD
 M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/P3041DS_NAND_SECURE_BOOT_defconfig
-F:	configs/P5020DS_NAND_SECURE_BOOT_defconfig
 F:	configs/P5040DS_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index 98322b2..4d62fc9 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -8,9 +8,7 @@ obj-y	+= corenet_ds.o
 obj-y	+= ddr.o
 obj-$(CONFIG_TARGET_P3041DS)	+= eth_hydra.o
 obj-$(CONFIG_TARGET_P4080DS)	+= eth_p4080.o
-obj-$(CONFIG_TARGET_P5020DS)	+= eth_hydra.o
 obj-$(CONFIG_TARGET_P5040DS)	+= eth_superhydra.o
 obj-$(CONFIG_TARGET_P3041DS)	+= p3041ds_ddr.o
 obj-$(CONFIG_TARGET_P4080DS)	+= p4080ds_ddr.o
-obj-$(CONFIG_TARGET_P5020DS)	+= p5020ds_ddr.o
 obj-$(CONFIG_TARGET_P5040DS)	+= p5040ds_ddr.o
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
deleted file mode 100644
index 112733b..0000000
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{0, 0, NULL}
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_1[] = {
-	{0, 0, NULL}
-};
diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg
deleted file mode 100644
index b09e409..0000000
--- a/board/freescale/corenet_ds/rcw_p5020ds.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for P5020DS.
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-0C540000 00000000 1E120000 00000000
-D8984A01 03002000 58000000 41000000
-00000000 00000000 00000000 10070000
-00000000 00000000 00000000 00000000
diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS
index c9f7fa3..6e940dd 100644
--- a/board/freescale/p1010rdb/MAINTAINERS
+++ b/board/freescale/p1010rdb/MAINTAINERS
@@ -4,30 +4,18 @@ S:	Maintained
 F:	board/freescale/p1010rdb/
 F:	include/configs/P1010RDB.h
 F:	configs/P1010RDB-PA_36BIT_NAND_defconfig
-F:	configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_36BIT_NOR_defconfig
-F:	configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_36BIT_SDCARD_defconfig
 F:	configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
-F:	configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_NAND_defconfig
-F:	configs/P1010RDB-PA_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_NOR_defconfig
-F:	configs/P1010RDB-PA_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_SDCARD_defconfig
 F:	configs/P1010RDB-PA_SPIFLASH_defconfig
-F:	configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_NAND_defconfig
-F:	configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_NOR_defconfig
-F:	configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_SDCARD_defconfig
 F:	configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
-F:	configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_NAND_defconfig
-F:	configs/P1010RDB-PB_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_NOR_defconfig
-F:	configs/P1010RDB-PB_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_SDCARD_defconfig
 F:	configs/P1010RDB-PB_SPIFLASH_defconfig
-F:	configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index accf2f2..4c3a03e 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -484,6 +484,7 @@ int checkboard(void)
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(struct bd_info *bis)
 {
 #ifdef CONFIG_TSEC_ENET
@@ -524,6 +525,7 @@ int board_eth_init(struct bd_info *bis)
 
 	return pci_eth_init(bis);
 }
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 void fdt_del_flexcan(void *blob)
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 4ee4573..fbaa6a6 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -69,8 +69,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/p1023rdb/Kconfig b/board/freescale/p1023rdb/Kconfig
deleted file mode 100644
index 1e4cd10..0000000
--- a/board/freescale/p1023rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1023RDB
-
-config SYS_BOARD
-	default "p1023rdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "P1023RDB"
-
-endif
diff --git a/board/freescale/p1023rdb/MAINTAINERS b/board/freescale/p1023rdb/MAINTAINERS
deleted file mode 100644
index c06bac6..0000000
--- a/board/freescale/p1023rdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-P1023RDB BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/p1023rdb/
-F:	include/configs/P1023RDB.h
-F:	configs/P1023RDB_defconfig
diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
deleted file mode 100644
index 78dc5d5..0000000
--- a/board/freescale/p1023rdb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y	+= p1023rdb.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
deleted file mode 100644
index dc7a909..0000000
--- a/board/freescale/p1023rdb/ddr.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-/* CONFIG_SYS_DDR_RAW_TIMING */
-/*
- * Hynix H5TQ1G83TFR-H9C
- */
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 1,
-	.rank_density = 536870912u,
-	.capacity = 536870912u,
-	.primary_sdram_width = 32,
-	.ec_sdram_width = 0,
-	.registered_dimm = 0,
-	.mirrored_dimm = 0,
-	.n_row_addr = 14,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 0,
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1875,
-	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
-	.taa_ps = 13125,
-	.twr_ps = 18000,
-	.trcd_ps = 13125,
-	.trrd_ps = 7500,
-	.trp_ps = 13125,
-	.tras_ps = 37500,
-	.trc_ps = 50625,
-	.trfc_ps = 160000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "Fixed DDR on board";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	int i;
-	popts->clk_adjust = 6;
-	popts->cpo_override = 0x1f;
-	popts->write_data_delay = 2;
-	popts->half_strength_driver_enable = 1;
-	/* Write leveling override */
-	popts->wrlvl_en = 1;
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-	popts->wrlvl_start = 0x8;
-	popts->trwt_override = 1;
-	popts->trwt = 0;
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
-		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
-	}
-}
diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
deleted file mode 100644
index 405fcd7..0000000
--- a/board/freescale/p1023rdb/law.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
-		LAW_TRGT_IF_DPAA_SWP_SRAM),
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
deleted file mode 100644
index b70ff68..0000000
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * Authors:  Roy Zang <tie-fei.zang@freescale.com>
- *           Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_portals.h>
-#include <fsl_qbman.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	/* Set ABSWP to implement conversion of addresses in the LBC */
-	setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	printf("Board: P1023 RDB\n");
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	setup_qbman_portals();
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
-	return gd->bus_clk;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
-	return gd->mem_clk;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	struct fsl_pq_mdio_info dtsec_mdio_info;
-
-	/*
-	 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
-	 * is not correct.
-	 */
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
-
-	dtsec_mdio_info.regs =
-		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
-	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
-
-	fm_info_set_mdio(FM1_DTSEC1,
-			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-	fm_info_set_mdio(FM1_DTSEC2,
-			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-
-#ifdef CONFIG_FMAN_ENET
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
-	fdt_fixup_fman_ethernet(blob);
-#endif
-#endif
-	return 0;
-}
-#endif
diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
deleted file mode 100644
index 9f0314d..0000000
--- a/board/freescale/p1023rdb/tlb.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_4M, 1),
-
-	/* W**G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 7, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 9, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_1M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_16K, 1),
-
-#ifdef CONFIG_SYS_RAMBOOT
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
-		      CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 12, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 13, BOOKE_PAGESZ_256M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
index 2f9640b..cd36150 100644
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -1,10 +1,5 @@
-if TARGET_P1020MBG		|| \
-	TARGET_P1020RDB_PC	|| \
+if	TARGET_P1020RDB_PC	|| \
 	TARGET_P1020RDB_PD	|| \
-	TARGET_P1020UTM		|| \
-	TARGET_P1021RDB		|| \
-	TARGET_P1024RDB		|| \
-	TARGET_P1025RDB		|| \
 	TARGET_P2020RDB
 
 config SYS_BOARD
diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
index c2e9247..b737b09 100644
--- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS
+++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
@@ -3,10 +3,6 @@ P1_P2_RDB_PC BOARD
 S:	Maintained
 F:	board/freescale/p1_p2_rdb_pc/
 F:	include/configs/p1_p2_rdb_pc.h
-F:	configs/P1020MBG-PC_defconfig
-F:	configs/P1020MBG-PC_36BIT_defconfig
-F:	configs/P1020MBG-PC_36BIT_SDCARD_defconfig
-F:	configs/P1020MBG-PC_SDCARD_defconfig
 F:	configs/P1020RDB-PC_defconfig
 F:	configs/P1020RDB-PC_36BIT_defconfig
 F:	configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -19,28 +15,6 @@ F:	configs/P1020RDB-PD_defconfig
 F:	configs/P1020RDB-PD_NAND_defconfig
 F:	configs/P1020RDB-PD_SDCARD_defconfig
 F:	configs/P1020RDB-PD_SPIFLASH_defconfig
-F:	configs/P1020UTM-PC_defconfig
-F:	configs/P1020UTM-PC_36BIT_defconfig
-F:	configs/P1020UTM-PC_36BIT_SDCARD_defconfig
-F:	configs/P1020UTM-PC_SDCARD_defconfig
-F:	configs/P1021RDB-PC_defconfig
-F:	configs/P1021RDB-PC_36BIT_defconfig
-F:	configs/P1021RDB-PC_36BIT_NAND_defconfig
-F:	configs/P1021RDB-PC_36BIT_SDCARD_defconfig
-F:	configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
-F:	configs/P1021RDB-PC_NAND_defconfig
-F:	configs/P1021RDB-PC_SDCARD_defconfig
-F:	configs/P1021RDB-PC_SPIFLASH_defconfig
-F:	configs/P1024RDB_defconfig
-F:	configs/P1024RDB_36BIT_defconfig
-F:	configs/P1024RDB_NAND_defconfig
-F:	configs/P1024RDB_SDCARD_defconfig
-F:	configs/P1024RDB_SPIFLASH_defconfig
-F:	configs/P1025RDB_defconfig
-F:	configs/P1025RDB_36BIT_defconfig
-F:	configs/P1025RDB_NAND_defconfig
-F:	configs/P1025RDB_SDCARD_defconfig
-F:	configs/P1025RDB_SPIFLASH_defconfig
 F:	configs/P2020RDB-PC_defconfig
 F:	configs/P2020RDB-PC_36BIT_defconfig
 F:	configs/P2020RDB-PC_36BIT_NAND_defconfig
diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
index b85cf02..86ff04e 100644
--- a/board/freescale/p1_p2_rdb_pc/README
+++ b/board/freescale/p1_p2_rdb_pc/README
@@ -4,10 +4,8 @@ P1_P2_RDB_PC represents a set of boards including
     P1020MSBG-PC
     P1020RDB-PC
     P1020RDB-PD
-    P1020UTM-PC
     P1021RDB-PC
     P1024RDB
-    P1025RDB
     P2020RDB-PC
 
 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 2346f6a..be803dd 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -14,9 +14,7 @@
 #include <asm/fsl_law.h>
 
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if	defined(CONFIG_P1020RDB_PROTO) || \
-	defined(CONFIG_TARGET_P1021RDB) || \
-	defined(CONFIG_TARGET_P1020UTM)
+#if	defined(CONFIG_P1020RDB_PROTO)
 /* Micron MT41J256M8_187E */
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 1,
@@ -146,8 +144,7 @@ dimm_params_t ddr_raw_timing = {
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 37500,
 };
-#elif	defined(CONFIG_TARGET_P1024RDB) || \
-	defined(CONFIG_TARGET_P1025RDB)
+#elif	defined(CONFIG_TARGET_P1024RDB)
 /*
  * Samsung K4B2G0846C-HCH9
  * The following timing are for "downshift"
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 7c703b3..4584f01 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -45,68 +45,12 @@
 #define GPIO_SLIC_PIN		30
 #define GPIO_SLIC_DATA		(1 << (31 - GPIO_SLIC_PIN))
 
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-#define GPIO_DDR_RST_PORT	1
-#define GPIO_DDR_RST_PIN	8
-#define GPIO_DDR_RST_DATA	(1 << (31 - GPIO_DDR_RST_PIN))
-
-#define GPIO_2BIT_MASK		(0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
-#endif
-
-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
-#define PCA_IOPORT_I2C_ADDR		0x23
-#define PCA_IOPORT_OUTPUT_CMD		0x2
-#define PCA_IOPORT_CFG_CMD		0x6
-#define PCA_IOPORT_QE_PIN_ENABLE	0xf8
-#define PCA_IOPORT_QE_TDM_ENABLE	0xf6
-#endif
-
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* GPIO */
 	{1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-	{1,   8, 1, 1, 0}, /* GPIO10/PB8  - DDR_RST */
-#endif
 	{0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
 	{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0},	/* RST_GETH_SW_N */
 	{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},	/* RST_SLIC_N */
-
-#ifdef CONFIG_TARGET_P1025RDB
-	/* QE_MUX_MDC */
-	{1,  19, 1, 0, 1}, /* QE_MUX_MDC               */
-
-	/* QE_MUX_MDIO */
-	{1,  20, 3, 0, 1}, /* QE_MUX_MDIO              */
-
-	/* UCC_1_MII */
-	{0, 23, 2, 0, 2}, /* CLK12 */
-	{0, 24, 2, 0, 1}, /* CLK9 */
-	{0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0      */
-	{0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1      */
-	{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2      */
-	{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
-	{0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0      */
-	{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1      */
-	{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
-	{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
-	{0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
-	{0, 13, 1, 0, 2}, /* ENET1_TX_ER               */
-	{0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B    */
-	{0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B    */
-	{0, 17, 2, 0, 2}, /* ENET1_CRS    */
-	{0, 16, 2, 0, 2}, /* ENET1_COL    */
-
-	/* UCC_5_RMII */
-	{1, 11, 2, 0, 1}, /* CLK13 */
-	{1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0      */
-	{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1      */
-	{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0      */
-	{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1      */
-	{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B    */
-	{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B    */
-	{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B    */
-#endif
-
 	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 };
 #endif
@@ -156,16 +100,6 @@ void board_gpio_init(void)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
 
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-	/* reset DDR3 */
-	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	udelay(1000);
-	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	udelay(1000);
-	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	/* disable CE_PB8 */
-	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
-#endif
 	/* Enable VSC7385 switch */
 	setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
 
@@ -316,6 +250,10 @@ int board_early_init_r(void)
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+	unsigned int vscfw_addr;
+	char *tmp;
+#endif
 
 	/*
 	 * Remap Boot flash region to caching-inhibited
@@ -338,9 +276,24 @@ int board_early_init_r(void)
 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
 		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+	/* If a VSC7385 microcode image is present, then upload it. */
+	tmp = env_get("vscfw_addr");
+	if (tmp) {
+		vscfw_addr = simple_strtoul(tmp, NULL, 16);
+		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+		if (vsc7385_upload_firmware((void *)vscfw_addr,
+					    CONFIG_VSC7385_IMAGE_SIZE))
+			puts("Failure uploading VSC7385 microcode.\n");
+	} else {
+		puts("No address specified for VSC7385 microcode.\n");
+	}
+#endif
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(struct bd_info *bis)
 {
 	struct fsl_pq_mdio_info mdio_info;
@@ -348,10 +301,6 @@ int board_eth_init(struct bd_info *bis)
 	ccsr_gur_t *gur __attribute__((unused)) =
 		(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int num = 0;
-#ifdef CONFIG_VSC7385_ENET
-	char *tmp;
-	unsigned int vscfw_addr;
-#endif
 
 #ifdef CONFIG_TSEC1
 	SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -375,19 +324,6 @@ int board_eth_init(struct bd_info *bis)
 		return 0;
 	}
 
-#ifdef CONFIG_VSC7385_ENET
-	/* If a VSC7385 microcode image is present, then upload it. */
-	tmp = env_get("vscfw_addr");
-	if (tmp) {
-		vscfw_addr = simple_strtoul(tmp, NULL, 16);
-		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
-		if (vsc7385_upload_firmware((void *) vscfw_addr,
-					CONFIG_VSC7385_IMAGE_SIZE))
-			puts("Failure uploading VSC7385 microcode.\n");
-	} else
-		puts("No address specified for VSC7385 microcode.\n");
-#endif
-
 	mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 	mdio_info.name = DEFAULT_MII_NAME;
 
@@ -405,50 +341,6 @@ int board_eth_init(struct bd_info *bis)
 
 	return pci_eth_init(bis);
 }
-
-#if defined(CONFIG_QE) && \
-	(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
-static void fdt_board_fixup_qe_pins(void *blob)
-{
-	unsigned int oldbus;
-	u8 val8;
-	int node;
-	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	if (hwconfig("qe")) {
-		/* For QE and eLBC pins multiplexing,
-		 * there is a PCA9555 device on P1025RDB.
-		 * It control the multiplex pins' functions,
-		 * and setting the PCA9555 can switch the
-		 * function between QE and eLBC.
-		 */
-		oldbus = i2c_get_bus_num();
-		i2c_set_bus_num(0);
-		if (hwconfig("tdm"))
-			val8 = PCA_IOPORT_QE_TDM_ENABLE;
-		else
-			val8 = PCA_IOPORT_QE_PIN_ENABLE;
-		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
-				1, &val8, 1);
-		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
-				1, &val8, 1);
-		i2c_set_bus_num(oldbus);
-		/* if run QE TDM, Set ABSWP to implement
-		 * conversion of addresses in the eLBC.
-		 */
-		if (hwconfig("tdm")) {
-			set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
-			set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
-			setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-		}
-	} else {
-		node = fdt_path_offset(blob, "/qe");
-		if (node >= 0)
-			fdt_del_node(blob, node);
-	}
-
-	return;
-}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
@@ -478,9 +370,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #ifdef CONFIG_QE
 	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
 			sizeof("okay"), 0);
-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
-	fdt_board_fixup_qe_pins(blob);
-#endif
 #endif
 
 #if defined(CONFIG_HAS_FSL_DR_USB)
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index e76c3e8..8aceceb 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 14971f0..fcd7a55 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -84,13 +84,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 
-#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 	/* 2G DDR on P1020MBG, map the second 1G */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
-#endif /* TARGET_P1020MBG */
+#endif
 #endif /* RAMBOOT/SPL */
 
 #ifdef CONFIG_SYS_INIT_L2_ADDR
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index da442fc..09dd88a 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -103,8 +103,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index f83d69b..e792295 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -94,8 +94,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index c197884..d8c2bbe 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -102,8 +102,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 07aab63..c64bd87 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -72,8 +72,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 64d2753..9aa0a9b 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig
index 2767195..53c651c 100644
--- a/board/google/chromebook_coral/Kconfig
+++ b/board/google/chromebook_coral/Kconfig
@@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_16384
 
 config PCIE_ECAM_BASE
-	default 0xf0000000
+	default 0xe0000000
 
 config EARLY_POST_CROS_EC
 	bool "Enable early post to Chrome OS EC"
diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile
index 6a27ce3..f7a0ca6 100644
--- a/board/google/chromebook_coral/Makefile
+++ b/board/google/chromebook_coral/Makefile
@@ -3,3 +3,4 @@
 # Copyright 2019 Google LLC
 
 obj-y	+= coral.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/google/chromebook_coral/baseboard_dptf.asl b/board/google/chromebook_coral/baseboard_dptf.asl
new file mode 100644
index 0000000..5da963a
--- /dev/null
+++ b/board/google/chromebook_coral/baseboard_dptf.asl
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+#define DPTF_CPU_PASSIVE	95
+#define DPTF_CPU_CRITICAL	105
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Battery"
+#define DPTF_TSR0_PASSIVE	120
+#define DPTF_TSR0_CRITICAL	125
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Ambient"
+#define DPTF_TSR1_PASSIVE	46
+#define DPTF_TSR1_CRITICAL	75
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"Charger"
+#define DPTF_TSR2_PASSIVE	58
+#define DPTF_TSR2_CRITICAL	90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 },	/* 3A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		3000,	/* PowerLimitMinimum */
+		12000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 12d4fe6..f5ae482 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -4,7 +4,24 @@
  */
 
 #include <common.h>
+#include <bloblist.h>
 #include <command.h>
+#include <dm.h>
+#include <log.h>
+#include <acpi/acpigen.h>
+#include <asm-generic/gpio.h>
+#include <asm/acpi_nhlt.h>
+#include <asm/intel_gnvs.h>
+#include <asm/intel_pinctrl.h>
+#include <dm/acpi.h>
+#include "variant_gpio.h"
+
+struct cros_gpio_info {
+	const char *linux_name;
+	enum cros_gpio_t type;
+	int gpio_num;
+	int flags;
+};
 
 int arch_misc_init(void)
 {
@@ -18,3 +35,122 @@ int board_run_command(const char *cmdline)
 
 	return 0;
 }
+
+int chromeos_get_gpio(const struct udevice *dev, const char *prop,
+		      enum cros_gpio_t type, struct cros_gpio_info *info)
+{
+	struct udevice *pinctrl;
+	struct gpio_desc desc;
+	int ret;
+
+	ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0);
+	if (ret == -ENOTBLK)
+		info->gpio_num = CROS_GPIO_VIRTUAL;
+	else if (ret)
+		return log_msg_ret("gpio", ret);
+	else
+		info->gpio_num = desc.offset;
+	info->linux_name = dev_read_string(desc.dev, "linux-name");
+	if (!info->linux_name)
+		return log_msg_ret("linux-name", -ENOENT);
+	info->type = type;
+	/* Get ACPI pin from GPIO library if available */
+	if (info->gpio_num != CROS_GPIO_VIRTUAL) {
+		pinctrl = dev_get_parent(desc.dev);
+		info->gpio_num = intel_pinctrl_get_acpi_pin(pinctrl,
+							    info->gpio_num);
+	}
+	info->flags = desc.flags & GPIOD_ACTIVE_LOW ? CROS_GPIO_ACTIVE_LOW :
+		CROS_GPIO_ACTIVE_HIGH;
+
+	return 0;
+}
+
+static int chromeos_acpi_gpio_generate(const struct udevice *dev,
+				       struct acpi_ctx *ctx)
+{
+	struct cros_gpio_info info[3];
+	int count, i;
+	int ret;
+
+	count = 3;
+	ret = chromeos_get_gpio(dev, "recovery-gpios", CROS_GPIO_REC, &info[0]);
+	if (ret)
+		return log_msg_ret("rec", ret);
+	ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP,
+				&info[1]);
+	if (ret)
+		return log_msg_ret("rec", ret);
+	ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE,
+				&info[2]);
+	if (ret)
+		return log_msg_ret("rec", ret);
+	acpigen_write_scope(ctx, "\\");
+	acpigen_write_name(ctx, "OIPG");
+	acpigen_write_package(ctx, count);
+	for (i = 0; i < count; i++) {
+		acpigen_write_package(ctx, 4);
+		acpigen_write_integer(ctx, info[i].type);
+		acpigen_write_integer(ctx, info[i].flags);
+		acpigen_write_integer(ctx, info[i].gpio_num);
+		acpigen_write_string(ctx, info[i].linux_name);
+		acpigen_pop_len(ctx);
+	}
+
+	acpigen_pop_len(ctx);
+	acpigen_pop_len(ctx);
+
+	return 0;
+}
+
+static int coral_write_acpi_tables(const struct udevice *dev,
+				   struct acpi_ctx *ctx)
+{
+	struct acpi_global_nvs *gnvs;
+	struct nhlt *nhlt;
+	const char *oem_id = "coral";
+	const char *oem_table_id = "coral";
+	u32 oem_revision = 3;
+	int ret;
+
+	gnvs = bloblist_find(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs));
+	if (!gnvs)
+		return log_msg_ret("bloblist", -ENOENT);
+
+	nhlt = nhlt_init();
+	if (!nhlt)
+		return -ENOMEM;
+
+	log_debug("Setting up NHLT\n");
+	ret = acpi_setup_nhlt(ctx, nhlt);
+	if (ret)
+		return log_msg_ret("setup", ret);
+
+	/* Update NHLT GNVS Data */
+	gnvs->nhla = (uintptr_t)ctx->current;
+	gnvs->nhll = nhlt_current_size(nhlt);
+
+	ret = nhlt_serialise_oem_overrides(ctx, nhlt, oem_id, oem_table_id,
+					   oem_revision);
+	if (ret)
+		return log_msg_ret("serialise", ret);
+
+	return 0;
+}
+
+struct acpi_ops coral_acpi_ops = {
+	.write_tables	= coral_write_acpi_tables,
+	.inject_dsdt	= chromeos_acpi_gpio_generate,
+};
+
+static const struct udevice_id coral_ids[] = {
+	{ .compatible = "google,coral" },
+	{ }
+};
+
+U_BOOT_DRIVER(coral_drv) = {
+	.name		= "coral",
+	.id		= UCLASS_BOARD,
+	.of_match	= coral_ids,
+	ACPI_OPS_PTR(&coral_acpi_ops)
+};
diff --git a/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat b/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
new file mode 100644
index 0000000..46c0efb
--- /dev/null
+++ b/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
diff --git a/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
new file mode 100644
index 0000000..6a7f2ce
--- /dev/null
+++ b/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
diff --git a/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
new file mode 100644
index 0000000..71d7648
--- /dev/null
+++ b/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
diff --git a/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
new file mode 100644
index 0000000..142ab35
--- /dev/null
+++ b/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
diff --git a/board/google/chromebook_coral/dsdt.asl b/board/google/chromebook_coral/dsdt.asl
new file mode 100644
index 0000000..b51e0b0
--- /dev/null
+++ b/board/google/chromebook_coral/dsdt.asl
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "variant_ec.h"
+#include "variant_gpio.h"
+#include <acpi/acpi_table.h>
+#include <asm/acpi/global_nvs.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	OEM_TABLE_ID,
+	0x20110725	// OEM revision
+)
+{
+	/* global NVS and variables */
+	#include <asm/arch/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <asm/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <asm/arch/acpi/northbridge.asl>
+			#include <asm/arch/acpi/southbridge.asl>
+			#include <asm/arch/acpi/pch_hda.asl>
+		}
+	}
+
+	/* Chrome OS specific */
+	#include <asm/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <asm/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <asm/acpi/cros_ec/superio.asl>
+		/* ACPI code for EC functions */
+		#include <asm/acpi/cros_ec/ec.asl>
+	}
+
+	/* Dynamic Platform Thermal Framework */
+	Scope (\_SB)
+	{
+		/* Per board variant specific definitions. */
+		#include "variant_dptf.asl"
+		/* Include soc specific DPTF changes */
+		#include <asm/arch/acpi/dptf.asl>
+		/* Include common dptf ASL files */
+		#include <asm/acpi/dptf/dptf.asl>
+	}
+}
diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
diff --git a/board/google/chromebook_coral/variant_dptf.asl b/board/google/chromebook_coral/variant_dptf.asl
new file mode 100644
index 0000000..943ebea
--- /dev/null
+++ b/board/google/chromebook_coral/variant_dptf.asl
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "baseboard_dptf.asl"
diff --git a/board/google/chromebook_coral/variant_ec.h b/board/google/chromebook_coral/variant_ec.h
new file mode 100644
index 0000000..7d5e1a6
--- /dev/null
+++ b/board/google/chromebook_coral/variant_ec.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+/*
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include "variant_gpio.h"
+#include <ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif
diff --git a/board/google/chromebook_coral/variant_gpio.h b/board/google/chromebook_coral/variant_gpio.h
new file mode 100644
index 0000000..f516d88
--- /dev/null
+++ b/board/google/chromebook_coral/variant_gpio.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <asm/arch/gpio.h>
+#include <ec_commands.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI	GPE0_DW1_11
+
+/* EC SMI */
+#define EC_SMI_GPI	GPIO_49
+
+/*
+ * On lidopen/lidclose GPIO_22 from North Community gets toggled and
+ * is used in _PRW to wake up device from sleep. GPIO_22 maps to
+ * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
+ * EDGE_SINGLE and INVERT.
+ */
+#define GPE_EC_WAKE	GPE0_DW1_22
+
+/* Write Protect and indication if EC is in RW code. */
+#define GPIO_PCH_WP	GPIO_75
+#define GPIO_EC_IN_RW	GPIO_41
+/* Determine if board is in final shipping mode. */
+#define GPIO_SHIP_MODE	GPIO_10
+
+/*  Memory SKU GPIOs. */
+#define MEM_CONFIG3	GPIO_45
+#define MEM_CONFIG2	GPIO_38
+#define MEM_CONFIG1	GPIO_102
+#define MEM_CONFIG0	GPIO_101
+
+/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
+#define DMIC_CONFIG_PIN	GPIO_17
+
+#ifndef __ASSEMBLY__
+
+enum cros_gpio_t {
+	CROS_GPIO_REC = 1,	 /* Recovery */
+
+	/* Developer; * deprecated (chromium:942901) */
+	CROS_GPIO_DEPRECATED_DEV = 2,
+	CROS_GPIO_WP = 3,	/* Write Protect */
+	CROS_GPIO_PE = 4,	/* Phase enforcement for final product */
+
+	CROS_GPIO_ACTIVE_LOW = 0,
+	CROS_GPIO_ACTIVE_HIGH = 1,
+
+	CROS_GPIO_VIRTUAL = -1,
+};
+#endif
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/board/intel/edison/edison-environment.txt b/board/intel/edison/edison-environment.txt
new file mode 100644
index 0000000..afe0092
--- /dev/null
+++ b/board/intel/edison/edison-environment.txt
@@ -0,0 +1,48 @@
+partitions=uuid_disk=${uuid_disk};name=u-boot0,start=1MiB,size=2MiB,uuid=${uuid_uboot0};name=u-boot-env0,size=1MiB,uuid=${uuid_uboot_env0};name=u-boot1,size=2MiB,uuid=${uuid_uboot1};name=u-boot-env1,size=1MiB,uuid=${uuid_uboot_env1};name=factory,size=1MiB,uuid=${uuid_factory};name=panic,size=24MiB,uuid=${uuid_panic};name=boot,size=32MiB,uuid=${uuid_boot};name=rootfs,size=1536MiB,uuid=${uuid_rootfs};name=update,size=768MiB,uuid=${uuid_update};name=home,size=-,uuid=${uuid_home};
+do_dfu_alt_info_mmc=setenv dfu_alt_info "ifwi${hardware_id} raw 0 8192 mmcpart 1;ifwib${hardware_id} raw 0 8192 mmcpart 2;u-boot0 part 0 1;u-boot-env0 part 0 2;u-boot1 part 0 3;u-boot-env1 part 0 4;boot part 0 7;rootfs part 0 8;update part 0 9;home part 0 10;vmlinuz fat 0 7;initrd fat 0 7"
+dfu_alt_info_ram=kernel ram ${loadaddr} 0x800000
+do_dfu_alt_info_ifwi=setenv dfu_alt_info "ifwi${hardware_id} raw 0 8192 mmcpart 1;ifwib${hardware_id} raw 0 8192 mmcpart 2"
+dfu_alt_info_reset=reset ram 0x0 0x0
+bootargs_console=console=ttyMFD2 earlyprintk=ttyMFD2,keep
+bootargs_debug=loglevel=4
+do_bootargs_rootfs=setenv bootargs_rootfs rootwait root=PARTUUID=${uuid_rootfs} rootfstype=ext4
+first_install_retry=0
+first_install_max_retries=3
+ota_update_retry=0
+ota_update_max_retries=3
+audio_codec_name=audio_codec="dummy"
+do_audio_support=setenv audio_support platform_mrfld_audio.${audio_codec_name}
+do_compute_target=if itest.b ${first_install_retry} -gt ${first_install_max_retries} || itest.b ${ota_update_retry} -gt ${ota_update_max_retries}; then echo "Switch to Rescue target"; setenv bootargs_target rescue; saveenv; fi
+mmc-bootargs=run do_bootargs_rootfs; run do_audio_support; setenv bootargs ${bootargs_rootfs} ${bootargs_console} ${bootargs_debug} g_multi.ethernet_config=${bootargs_ethconfig} systemd.unit=${bootargs_target}.target hardware_id=${hardware_id} g_multi.iSerialNumber=${serial#} g_multi.dev_addr=${usb0addr} ${audio_support}
+loadaddr=0x100000
+load_kernel=fatload mmc 0:7 ${loadaddr} vmlinuz
+do_partition_done=0
+do_partition=if itest.b ${do_partition_done} -eq 1; then echo "Partitioning already done..."; else run do_force_partition ; fi
+do_force_partition=echo "Partitioning using GPT"; gpt write mmc 0 ${partitions} ; mmc rescan; setenv do_partition_done 1 ; saveenv
+do_flash_ifwi=run do_dfu_alt_info_ifwi ; dfu 0 mmc 0 $dfu_to_sec
+do_flash_os=if itest.b ${do_flash_os_done} -eq 1 ; then echo "Flashing already done..." ; else run do_force_flash_os; fi
+do_force_flash_os=run do_dfu_alt_info_mmc ; sleep 1 ; setenv do_flash_os_done 1 ; saveenv ; dfu 0 mmc 0 $dfu_to_sec
+do_flashall=run do_partition;run do_flash_ifwi;run do_flash_os
+do_dnx=setenv dfu_alt_info ${dfu_alt_info_ram};dfu 0 ram 0 ram;run bootcmd
+init_dfu=run do_dfu_alt_info_mmc ; saveenv
+bootcmd=echo "Target:${target_name}"; run do_partition; run do_handle_bootargs_mode;
+do_handle_bootargs_mode=run do_preprocess_bootargs_mode; if itest.s $bootargs_mode == "ota" ; then run do_ota; fi; if itest.s $bootargs_mode == "boot" ; then run do_boot; fi; if itest.s $bootargs_mode == "flash"; then run do_flash; fi; run do_fallback; exit;
+do_preprocess_bootargs_mode=if env exists bootargs_mode ; then ; else setenv bootargs_mode "boot" ;fi;
+do_fallback=echo "Unknown boot mode: $bootargs_mode"; env delete -f bootargs_mode; saveenv; echo "Resetting to default boot mode and reboot..."; reset;
+do_boot=run boot_target_cmd;
+do_flash=run do_force_flash_os;
+ota_done=0
+ota_script_addr=0x100000
+do_ota_init=setenv ota_status 1 ; env delete -f bootargs_mode
+do_load_ota_scr=if fatload mmc 0:9 $ota_script_addr ota_update.scr ; then setenv ota_status 0 ; else setenv ota_status 1 ; fi
+do_source_ota_scr=if test $ota_status -eq 0 ; then if source $ota_script_addr ; then setenv ota_status 0 ; else setenv ota_status 2 ; fi ; fi
+do_ota_clean=saveenv ; reset
+do_ota=run do_ota_init ; run do_load_ota_scr ; run do_source_ota_scr ; run do_ota_clean
+target_name=blank
+bootdelay=1
+do_flash_os_done=1
+bootargs_target=multi-user
+bootargs_ethconfig=cdc
+dfu_to_sec=3
+do_probe_dfu=run do_dfu_alt_info_mmc ; dfu 0 mmc 0 $dfu_to_sec
+boot_target_cmd=run do_flash_os;run do_probe_dfu;run do_compute_target;run mmc-bootargs;run load_kernel;zboot ${loadaddr}
diff --git a/board/intel/edison/edison-osip.dat b/board/intel/edison/edison-osip.dat
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/board/intel/edison/edison-osip.dat
diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig
index 94075ce..bbafabd 100644
--- a/board/keymile/km83xx/Kconfig
+++ b/board/keymile/km83xx/Kconfig
@@ -1,3 +1,20 @@
+menu "KM 83xx Options"
+	depends on MPC83xx
+
+config KM_ENABLE_FULL_DM_DTS_SUPPORT
+	bool "enable full DM/DTS support for KM 83xx boards"
+	default y
+	select CMD_DM
+	select DM
+	select DM_ETH
+	select DM_MDIO
+	select DM_SERIAL
+	select OF_CONTROL
+	select PINCTRL
+	select PINCTRL_QE
+	select PHYLIB
+endmenu
+
 if TARGET_KMETER1
 
 config SYS_BOARD
diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
index d9483c7..9268719 100644
--- a/board/keymile/km83xx/MAINTAINERS
+++ b/board/keymile/km83xx/MAINTAINERS
@@ -1,5 +1,6 @@
 KM83XX BOARD
 M:	Holger Brunck <holger.brunck@hitachi-powergrids.com>
+M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 F:	board/keymile/km83xx/
 F:	include/configs/km8360.h
@@ -7,12 +8,24 @@ F:	configs/kmcoge5ne_defconfig
 F:	configs/kmeter1_defconfig
 F:	include/configs/tuxx1.h
 F:	configs/kmopti2_defconfig
+F:	configs/kmsupx5_defconfig
 F:	configs/kmtepr2_defconfig
 F:	configs/kmtegr1_defconfig
 F:	configs/tuge1_defconfig
 F:	configs/tuxx1_defconfig
-
-KMSUPX5 BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	configs/kmsupx5_defconfig
+F:	arch/powerpc/dts/km8309-uboot.dtsi
+F:	arch/powerpc/dts/km8321-uboot.dtsi
+F:	arch/powerpc/dts/km8321.dtsi
+F:	arch/powerpc/dts/km836x-uboot.dtsi
+F:	arch/powerpc/dts/km836x.dtsi
+F:	arch/powerpc/dts/kmcoge5ne-uboot.dtsi
+F:	arch/powerpc/dts/kmcoge5ne.dts
+F:	arch/powerpc/dts/kmeter1-uboot.dtsi
+F:	arch/powerpc/dts/kmeter1.dts
+F:	arch/powerpc/dts/kmopti2.dts
+F:	arch/powerpc/dts/kmsupc5.dts
+F:	arch/powerpc/dts/kmsupm5.dts
+F:	arch/powerpc/dts/kmtegr1.dts
+F:	arch/powerpc/dts/kmtepr2.dts
+F:	arch/powerpc/dts/kmtuge1.dts
+F:	arch/powerpc/dts/kmtuxa1.dts
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 0aad452..8669715 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -36,70 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* port pin dir open_drain assign */
-#if defined(CONFIG_ARCH_MPC8360)
-	/* MDIO */
-	{0,  1, 3, 0, 2}, /* MDIO */
-	{0,  2, 1, 0, 1}, /* MDC */
-
-	/* UCC4 - UEC */
-	{1, 14, 1, 0, 1}, /* TxD0 */
-	{1, 15, 1, 0, 1}, /* TxD1 */
-	{1, 20, 2, 0, 1}, /* RxD0 */
-	{1, 21, 2, 0, 1}, /* RxD1 */
-	{1, 18, 1, 0, 1}, /* TX_EN */
-	{1, 26, 2, 0, 1}, /* RX_DV */
-	{1, 27, 2, 0, 1}, /* RX_ER */
-	{1, 24, 2, 0, 1}, /* COL */
-	{1, 25, 2, 0, 1}, /* CRS */
-	{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
-	{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
-
-	/* DUART - UART2 */
-	{5,  0, 1, 0, 2}, /* UART2_SOUT */
-	{5,  2, 1, 0, 1}, /* UART2_RTS */
-	{5,  3, 2, 0, 2}, /* UART2_SIN */
-	{5,  1, 2, 0, 3}, /* UART2_CTS */
-#elif !defined(CONFIG_ARCH_MPC8309)
-	/* Local Bus */
-	{0, 16, 1, 0, 3}, /* LA00 */
-	{0, 17, 1, 0, 3}, /* LA01 */
-	{0, 18, 1, 0, 3}, /* LA02 */
-	{0, 19, 1, 0, 3}, /* LA03 */
-	{0, 20, 1, 0, 3}, /* LA04 */
-	{0, 21, 1, 0, 3}, /* LA05 */
-	{0, 22, 1, 0, 3}, /* LA06 */
-	{0, 23, 1, 0, 3}, /* LA07 */
-	{0, 24, 1, 0, 3}, /* LA08 */
-	{0, 25, 1, 0, 3}, /* LA09 */
-	{0, 26, 1, 0, 3}, /* LA10 */
-	{0, 27, 1, 0, 3}, /* LA11 */
-	{0, 28, 1, 0, 3}, /* LA12 */
-	{0, 29, 1, 0, 3}, /* LA13 */
-	{0, 30, 1, 0, 3}, /* LA14 */
-	{0, 31, 1, 0, 3}, /* LA15 */
-
-	/* MDIO */
-	{3,  4, 3, 0, 2}, /* MDIO */
-	{3,  5, 1, 0, 2}, /* MDC */
-
-	/* UCC4 - UEC */
-	{1, 18, 1, 0, 1}, /* TxD0 */
-	{1, 19, 1, 0, 1}, /* TxD1 */
-	{1, 22, 2, 0, 1}, /* RxD0 */
-	{1, 23, 2, 0, 1}, /* RxD1 */
-	{1, 26, 2, 0, 1}, /* RxER */
-	{1, 28, 2, 0, 1}, /* Rx_DV */
-	{1, 30, 1, 0, 1}, /* TxEN */
-	{1, 31, 2, 0, 1}, /* CRS */
-	{3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
-#endif
-
-	/* END of table */
-	{0,  0, 0, 0, QE_IOP_TAB_END},
-};
-
 static int piggy_present(void)
 {
 	struct km_bec_fpga __iomem *base =
diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c
index 91afcdd..8054511 100644
--- a/board/renesas/condor/condor.c
+++ b/board/renesas/condor/condor.c
@@ -18,15 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_init(void)
 {
 	/* adress of boot parameters */
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index c8f4b21..9993f5b 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -30,10 +30,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
 #define GSX_MSTP112		BIT(12)	/* 3DG */
 #define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
 #define DVFS_MSTP926		BIT(26)
@@ -75,23 +71,10 @@ int board_init(void)
 }
 
 #define RST_BASE	0xE6160000
-#define RST_CA57RESCNT	(RST_BASE + 0x40)
 #define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_RSTOUTCR	(RST_BASE + 0x58)
-#define RST_CA57_CODE	0xA5A5000F
 #define RST_CA53_CODE	0x5A5A000F
 
 void reset_cpu(ulong addr)
 {
-	unsigned long midr, cputype;
-
-	asm volatile("mrs %0, midr_el1" : "=r" (midr));
-	cputype = (midr >> 4) & 0xfff;
-
-	if (cputype == 0xd03)
-		writel(RST_CA53_CODE, RST_CA53RESCNT);
-	else if (cputype == 0xd07)
-		writel(RST_CA57_CODE, RST_CA57RESCNT);
-	else
-		hang();
+	writel(RST_CA53_CODE, RST_CA53RESCNT);
 }
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
index b6531f6..c8d1805 100644
--- a/board/renesas/ebisu/ebisu.c
+++ b/board/renesas/ebisu/ebisu.c
@@ -29,15 +29,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_init(void)
 {
 	/* adress of boot parameters */
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 947bdae..c78c2a4 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -31,10 +31,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
 #define DVFS_MSTP926		BIT(26)
 #define HSUSB_MSTP704		BIT(4)	/* HSUSB */
 
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index 07bc1ec..efbffa0 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -29,10 +29,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
 #define DVFS_MSTP926		BIT(26)
 #define HSUSB_MSTP704		BIT(4)	/* HSUSB */
 
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 71e2b75..a5cf0b6 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -711,7 +711,7 @@ int g_dnl_board_usb_cable_connected(void)
 
 	ret = generic_phy_init(&phy);
 	if (ret) {
-		pr_err("failed to init %s USB PHY\n", dev->name);
+		pr_debug("failed to init %s USB PHY\n", dev->name);
 		return ret;
 	}
 
diff --git a/board/sunxi/mksunxi_fit_atf.sh b/board/sunxi/mksunxi_fit_atf.sh
deleted file mode 100755
index 88ad719..0000000
--- a/board/sunxi/mksunxi_fit_atf.sh
+++ /dev/null
@@ -1,87 +0,0 @@
-#!/bin/sh
-#
-# script to generate FIT image source for 64-bit sunxi boards with
-# ARM Trusted Firmware and multiple device trees (given on the command line)
-#
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
-
-[ -z "$BL31" ] && BL31="bl31.bin"
-
-if [ ! -f $BL31 ]; then
-	echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
-	echo "Please read the section on ARM Trusted Firmware (ATF) in board/sunxi/README.sunxi64" >&2
-	BL31=/dev/null
-fi
-
-if grep -q "^CONFIG_MACH_SUN50I_H6=y" .config; then
-	BL31_ADDR=0x104000
-else
-	BL31_ADDR=0x44000
-fi
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
-	description = "Configuration to load ATF before U-Boot";
-	#address-cells = <1>;
-
-	images {
-		uboot {
-			description = "U-Boot (64-bit)";
-			data = /incbin/("u-boot-nodtb.bin");
-			type = "standalone";
-			arch = "arm64";
-			compression = "none";
-			load = <0x4a000000>;
-		};
-		atf {
-			description = "ARM Trusted Firmware";
-			data = /incbin/("$BL31");
-			type = "firmware";
-			arch = "arm64";
-			compression = "none";
-			load = <$BL31_ADDR>;
-			entry = <$BL31_ADDR>;
-		};
-__HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
-	cat << __FDT_IMAGE_EOF
-		fdt_$cnt {
-			description = "$(basename $dtname .dtb)";
-			data = /incbin/("$dtname");
-			type = "flat_dt";
-			compression = "none";
-		};
-__FDT_IMAGE_EOF
-	cnt=$((cnt+1))
-done
-
-cat << __CONF_HEADER_EOF
-	};
-	configurations {
-		default = "config_1";
-
-__CONF_HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
-	cat << __CONF_SECTION_EOF
-		config_$cnt {
-			description = "$(basename $dtname .dtb)";
-			firmware = "uboot";
-			loadables = "atf";
-			fdt = "fdt_$cnt";
-		};
-__CONF_SECTION_EOF
-	cnt=$((cnt+1))
-done
-
-cat << __ITS_EOF
-	};
-};
-__ITS_EOF
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index e100adf..219c871 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -5,3 +5,4 @@ F:	board/ti/am335x/
 F:	include/configs/am335x_evm.h
 F:	configs/am335x_boneblack_vboot_defconfig
 F:	configs/am335x_evm_defconfig
+F:	configs/am335x_evm_spiboot_defconfig
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index ebaa6fa..7925b76 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -117,6 +117,13 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
 }
 #endif
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	detect_enable_hyperflash(spl_image->fdt_addr);
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 73fc1be..c80d0a8 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -41,7 +41,7 @@ config XILINX_PS_INIT_FILE
 endif
 
 config XILINX_OF_BOARD_DTB_ADDR
-	hex
+	hex "Default DTB pickup address"
 	default 0x1000 if ARCH_VERSAL
 	default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
 	depends on OF_BOARD || OF_SEPARATE
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index eab389d..b0f60c4 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -44,7 +44,7 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
 void *board_fdt_blob_setup(void)
 {
-	static void *fdt_blob;
+	void *fdt_blob;
 
 #if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR)
 	fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index b4e7301..28f067a 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -9,6 +9,7 @@
 #include <cpu_func.h>
 #include <debug_uart.h>
 #include <env.h>
+#include <env_internal.h>
 #include <init.h>
 #include <log.h>
 #include <net.h>
@@ -38,181 +39,156 @@
 
 #include "pm_cfg_obj.h"
 
+#define ZYNQMP_VERSION_SIZE	7
+#define EFUSE_VCU_DIS_MASK     0x100
+#define EFUSE_VCU_DIS_SHIFT    8
+#define EFUSE_GPU_DIS_MASK     0x20
+#define EFUSE_GPU_DIS_SHIFT    5
+#define IDCODE2_PL_INIT_MASK   0x200
+#define IDCODE2_PL_INIT_SHIFT  9
+
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-    !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
 
+enum {
+	ZYNQMP_VARIANT_EG = BIT(0U),
+	ZYNQMP_VARIANT_EV = BIT(1U),
+	ZYNQMP_VARIANT_CG = BIT(2U),
+	ZYNQMP_VARIANT_DR = BIT(3U),
+};
+
 static const struct {
 	u32 id;
-	u32 ver;
-	char *name;
-	bool evexists;
+	u8 device;
+	u8 variants;
 } zynqmp_devices[] = {
 	{
-		.id = 0x10,
-		.name = "3eg",
-	},
-	{
-		.id = 0x10,
-		.ver = 0x2c,
-		.name = "3cg",
-	},
-	{
-		.id = 0x11,
-		.name = "2eg",
-	},
-	{
-		.id = 0x11,
-		.ver = 0x2c,
-		.name = "2cg",
+		.id = 0x04711093,
+		.device = 2,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x20,
-		.name = "5ev",
-		.evexists = 1,
+		.id = 0x04710093,
+		.device = 3,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x20,
-		.ver = 0x100,
-		.name = "5eg",
-		.evexists = 1,
+		.id = 0x04721093,
+		.device = 4,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x20,
-		.ver = 0x12c,
-		.name = "5cg",
-		.evexists = 1,
+		.id = 0x04720093,
+		.device = 5,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x21,
-		.name = "4ev",
-		.evexists = 1,
+		.id = 0x04739093,
+		.device = 6,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x21,
-		.ver = 0x100,
-		.name = "4eg",
-		.evexists = 1,
+		.id = 0x04730093,
+		.device = 7,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x21,
-		.ver = 0x12c,
-		.name = "4cg",
-		.evexists = 1,
+		.id = 0x04738093,
+		.device = 9,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.name = "7ev",
-		.evexists = 1,
+		.id = 0x04740093,
+		.device = 11,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.ver = 0x100,
-		.name = "7eg",
-		.evexists = 1,
+		.id = 0x04750093,
+		.device = 15,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.ver = 0x12c,
-		.name = "7cg",
-		.evexists = 1,
+		.id = 0x04759093,
+		.device = 17,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x38,
-		.name = "9eg",
+		.id = 0x04758093,
+		.device = 19,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x38,
-		.ver = 0x2c,
-		.name = "9cg",
+		.id = 0x047E1093,
+		.device = 21,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x39,
-		.name = "6eg",
+		.id = 0x047E3093,
+		.device = 23,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x39,
-		.ver = 0x2c,
-		.name = "6cg",
-	},
-	{
-		.id = 0x40,
-		.name = "11eg",
-	},
-	{ /* For testing purpose only */
-		.id = 0x50,
-		.ver = 0x2c,
-		.name = "15cg",
+		.id = 0x047E5093,
+		.device = 25,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x50,
-		.name = "15eg",
+		.id = 0x047E4093,
+		.device = 27,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x58,
-		.name = "19eg",
+		.id = 0x047E0093,
+		.device = 28,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x59,
-		.name = "17eg",
+		.id = 0x047E2093,
+		.device = 29,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x61,
-		.name = "21dr",
+		.id = 0x047E6093,
+		.device = 39,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x63,
-		.name = "23dr",
+		.id = 0x047FD093,
+		.device = 43,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x65,
-		.name = "25dr",
+		.id = 0x047F8093,
+		.device = 46,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x64,
-		.name = "27dr",
+		.id = 0x047FF093,
+		.device = 47,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x60,
-		.name = "28dr",
+		.id = 0x047FB093,
+		.device = 48,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x62,
-		.name = "29dr",
-	},
-	{
-		.id = 0x66,
-		.name = "39dr",
-	},
-	{
-		.id = 0x7b,
-		.name = "48dr",
-	},
-	{
-		.id = 0x7e,
-		.name = "49dr",
+		.id = 0x047FE093,
+		.device = 49,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 };
-#endif
 
-#define ZYNQMP_VERSION_SIZE		9
-#define ZYNQMP_PL_STATUS_BIT		9
-#define ZYNQMP_IPDIS_VCU_BIT		8
-#define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
-#define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)
-#define ZYNQMP_CSU_VCUDIS_VER_MASK	ZYNQMP_CSU_VERSION_MASK & \
-					~BIT(ZYNQMP_IPDIS_VCU_BIT)
-#define MAX_VARIANTS_EV			3
-
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-	!defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
-	u32 i, id, ver, j;
-	char *buf;
-	static char name[ZYNQMP_VERSION_SIZE];
+	u32 i;
+	u32 idcode, idcode2;
+	char name[ZYNQMP_VERSION_SIZE];
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
 	xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
@@ -226,61 +202,71 @@ static char *zynqmp_get_silicon_idcode_name(void)
 	 * payload[2][29] = PL_INIT
 	 */
 
-	/* Get IDCODE field */
-	id = ret_payload[1];
-	id &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | ZYNQMP_CSU_IDCODE_SVD_MASK;
-	id >>=	ZYNQMP_CSU_IDCODE_SVD_SHIFT;
-
-	/* Shift silicon version info */
-	ver = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
-
-	debug("%s, ID: 0x%0X, Ver: 0x%0X\r\n", __func__, id, ver);
+	idcode  = ret_payload[1];
+	idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+	debug("%s, IDCODE: 0x%0X, IDCODE2: 0x%0X\r\n", __func__, idcode,
+	      idcode2);
 
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-		if (zynqmp_devices[i].id == id) {
-			if (zynqmp_devices[i].evexists &&
-			    !(ver & ZYNQMP_PL_STATUS_MASK))
-				break;
-			if (zynqmp_devices[i].ver == (ver &
-			    ZYNQMP_CSU_VERSION_MASK))
-				break;
-		}
+		if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
+			break;
 	}
 
 	if (i >= ARRAY_SIZE(zynqmp_devices))
 		return "unknown";
 
-	strncat(name, "zu", 2);
-	if (!zynqmp_devices[i].evexists ||
-	    (ver & ZYNQMP_PL_STATUS_MASK)) {
-		strncat(name, zynqmp_devices[i].name,
-			ZYNQMP_VERSION_SIZE - 3);
-		return name;
-	}
-
-	/*
-	 * Here we are means, PL not powered up and ev variant
-	 * exists. So, we need to ignore VCU disable bit(8) in
-	 * version and findout if its CG or EG/EV variant.
-	 */
-	for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
-		if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
-		    (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
-			strncat(name, zynqmp_devices[i].name,
-				ZYNQMP_VERSION_SIZE - 3);
-			break;
+	/* Add device prefix to the name */
+	strncpy(name, "zu", ZYNQMP_VERSION_SIZE);
+	strncat(&name[2], simple_itoa(zynqmp_devices[i].device), 2);
+
+	if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
+		/* Devices with EV variant might be EG/CG/EV family */
+		if (idcode2 & IDCODE2_PL_INIT_MASK) {
+			u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
+				      EFUSE_VCU_DIS_SHIFT) << 1 |
+				     ((idcode2 & EFUSE_GPU_DIS_MASK) >>
+				      EFUSE_GPU_DIS_SHIFT);
+
+			/*
+			 * Get family name based on extended idcode values as
+			 * determined on UG1087, EXTENDED_IDCODE register
+			 * description
+			 */
+			switch (family) {
+			case 0x00:
+				strncat(name, "ev", 2);
+				break;
+			case 0x10:
+				strncat(name, "eg", 2);
+				break;
+			case 0x11:
+				strncat(name, "cg", 2);
+				break;
+			default:
+				/* Do not append family name*/
+				break;
+			}
+		} else {
+			/*
+			 * When PL powered down the VCU Disable efuse cannot be
+			 * read. So, ignore the bit and just findout if it is CG
+			 * or EG/EV variant.
+			 */
+			strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
+				"e", 2);
 		}
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
+		/* Devices with CG variant might be EG or CG family */
+		strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
+		strncat(name, "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
+		strncat(name, "dr", 2);
+	} else {
+		debug("Variant not identified\n");
 	}
 
-	if (j >= MAX_VARIANTS_EV)
-		return "unknown";
-
-	if (strstr(name, "eg") || strstr(name, "ev")) {
-		buf = strstr(name, "e");
-		*buf = '\0';
-	}
-
-	return name;
+	return strdup(name);
 }
 #endif
 
@@ -342,9 +328,7 @@ int board_init(void)
 	/* Bug in ROM sets wrong value in this register */
 	writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
 
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
-    defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 	zynqmppl.name = zynqmp_get_silicon_idcode_name();
 	printf("Chip ID:\t%s\n", zynqmppl.name);
 	fpga_init();
@@ -423,10 +407,8 @@ int dram_init(void)
 #else
 int dram_init_banksize(void)
 {
-#if defined(CONFIG_NR_DRAM_BANKS)
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
-#endif
 
 	mem_map_fill();
 
@@ -446,6 +428,24 @@ void reset_cpu(ulong addr)
 {
 }
 
+static u8 __maybe_unused zynqmp_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg = 0;
+	int ret;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
+	if (ret)
+		return -EINVAL;
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
 #if defined(CONFIG_BOARD_LATE_INIT)
 static const struct {
 	u32 bit;
@@ -529,24 +529,6 @@ static int set_fdtfile(void)
 	return 0;
 }
 
-static u8 zynqmp_get_bootmode(void)
-{
-	u8 bootmode;
-	u32 reg = 0;
-	int ret;
-
-	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
-	if (ret)
-		return -EINVAL;
-
-	if (reg >> BOOT_MODE_ALT_SHIFT)
-		reg >>= BOOT_MODE_ALT_SHIFT;
-
-	bootmode = reg & BOOT_MODES_MASK;
-
-	return bootmode;
-}
-
 int board_late_init(void)
 {
 	u8 bootmode;
@@ -691,3 +673,37 @@ int checkboard(void)
 	puts("Board: Xilinx ZynqMP\n");
 	return 0;
 }
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = zynqmp_get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case NAND_MODE:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+			return ENVL_NAND;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		return ENVL_UNKNOWN;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case JTAG_MODE:
+	default:
+		return ENVL_NOWHERE;
+	}
+}