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| author | Tom Rini <trini@konsulko.com> | 2021-02-23 10:45:55 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-02-23 10:45:55 -0500 |
| commit | cbe607b920bc0827d8fe379ed4f5ae4e2058513e (patch) | |
| tree | b8cdbb8856766675f37bb92f27ab9c662fa647f9 /board/xilinx/zynqmp/zynqmp.c | |
| parent | 8f7a16aac36c2a38956bd04b53cb7b94b7a70180 (diff) | |
| parent | d9aa19efa8a6c20d51b7884de0a7f8dae3f835d2 (diff) | |
| download | u-boot-cbe607b920bc0827d8fe379ed4f5ae4e2058513e.zip u-boot-cbe607b920bc0827d8fe379ed4f5ae4e2058513e.tar.gz u-boot-cbe607b920bc0827d8fe379ed4f5ae4e2058513e.tar.bz2 | |
Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblazeWIP/23Feb2021
Xilinx changes for v2021.04-rc3
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
Diffstat (limited to 'board/xilinx/zynqmp/zynqmp.c')
| -rw-r--r-- | board/xilinx/zynqmp/zynqmp.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 43e322f..4466717 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -329,6 +329,7 @@ int board_init(void) if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, zynqmp_pm_cfg_obj_size); + printf("Silicon version:\t%d\n", zynqmp_get_silicon_version()); #else if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) xilinx_read_eeprom(); @@ -496,11 +497,7 @@ static int reset_reason(void) env_set("reset_reason", reason); - ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0); - if (ret) - return -EINVAL; - - return ret; + return 0; } static int set_fdtfile(void) |