Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x

1 files changed, 21 insertions, 11 deletions

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 28f067a..731285a 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -40,12 +40,12 @@
 #include "pm_cfg_obj.h"
 
 #define ZYNQMP_VERSION_SIZE	7
-#define EFUSE_VCU_DIS_MASK     0x100
-#define EFUSE_VCU_DIS_SHIFT    8
-#define EFUSE_GPU_DIS_MASK     0x20
-#define EFUSE_GPU_DIS_SHIFT    5
-#define IDCODE2_PL_INIT_MASK   0x200
-#define IDCODE2_PL_INIT_SHIFT  9
+#define EFUSE_VCU_DIS_MASK	0x100
+#define EFUSE_VCU_DIS_SHIFT	8
+#define EFUSE_GPU_DIS_MASK	0x20
+#define EFUSE_GPU_DIS_SHIFT	5
+#define IDCODE2_PL_INIT_MASK	0x200
+#define IDCODE2_PL_INIT_SHIFT	9
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -100,7 +100,7 @@ static const struct {
 	{
 		.id = 0x04738093,
 		.device = 9,
-		.variants = ZYNQMP_VARIANT_EG,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
 		.id = 0x04740093,
@@ -190,8 +190,13 @@ static char *zynqmp_get_silicon_idcode_name(void)
 	u32 idcode, idcode2;
 	char name[ZYNQMP_VERSION_SIZE];
 	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
 
-	xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
+	ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
+	if (ret) {
+		debug("%s: Getting chipid failed\n", __func__);
+		return "unknown";
+	}
 
 	/*
 	 * Firmware returns:
@@ -204,7 +209,7 @@ static char *zynqmp_get_silicon_idcode_name(void)
 
 	idcode  = ret_payload[1];
 	idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
-	debug("%s, IDCODE: 0x%0X, IDCODE2: 0x%0X\r\n", __func__, idcode,
+	debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
 	      idcode2);
 
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
@@ -216,8 +221,10 @@ static char *zynqmp_get_silicon_idcode_name(void)
 		return "unknown";
 
 	/* Add device prefix to the name */
-	strncpy(name, "zu", ZYNQMP_VERSION_SIZE);
-	strncat(&name[2], simple_itoa(zynqmp_devices[i].device), 2);
+	ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
+		       zynqmp_devices[i].device);
+	if (ret < 0)
+		return "unknown";
 
 	if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
 		/* Devices with EV variant might be EG/CG/EV family */
@@ -321,6 +328,9 @@ int board_init(void)
 	if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 		zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 						zynqmp_pm_cfg_obj_size);
+#else
+	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
+		xilinx_read_eeprom();
 #endif
 
 	printf("EL Level:\tEL%d\n", current_el());