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| author | Tom Rini <trini@konsulko.com> | 2019-05-21 07:13:35 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-21 07:13:35 -0400 |
| commit | e1a2ed7180adeefb6164239a18249dca5701319d (patch) | |
| tree | 4a9d085f3154fb848c9ccfc391d87f39fd43c29f /board/tqc/tqm834x/tqm834x.c | |
| parent | ffbad25b3221fd1b0cd0aff1128d57fcb279e020 (diff) | |
| parent | d494cdb97e18a30214d0414376d4eacdf82224fe (diff) | |
| download | u-boot-e1a2ed7180adeefb6164239a18249dca5701319d.zip u-boot-e1a2ed7180adeefb6164239a18249dca5701319d.tar.gz u-boot-e1a2ed7180adeefb6164239a18249dca5701319d.tar.bz2 | |
Merge git://git.denx.de/u-boot-mpc83xx
- Update MPC83xx platform support to current best practices, etc.
Diffstat (limited to 'board/tqc/tqm834x/tqm834x.c')
| -rw-r--r-- | board/tqc/tqm834x/tqm834x.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 7c92f4f..04941b2 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -72,13 +72,13 @@ int dram_init(void) int cs; /* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE; im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); /* set CS bounds to maximum size */ for(cs = 0; cs < 4; ++cs) { set_cs_bounds(cs, - CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS), DDR_MAX_SIZE_PER_CS); set_cs_config(cs, INITIAL_CS_CONFIG); @@ -102,7 +102,7 @@ int dram_init(void) debug("\nDetecting Bank%d\n", cs); bank_size = get_ddr_bank_size(cs, - (long *)(CONFIG_SYS_DDR_BASE + size)); + (long *)(CONFIG_SYS_SDRAM_BASE + size)); size += bank_size; debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); @@ -235,8 +235,8 @@ static int detect_num_flash_banks(void) debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks); /* set OR0 and BR0 */ - set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH | - (-(total_size) & OR_GPCM_AM)); + set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | + OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM)); set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | (BR_MS_GPCM | BR_PS_32 | BR_V)); |