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| author | Igor Opaniuk <igor.opaniuk@toradex.com> | 2019-12-03 14:04:47 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-12-06 12:09:30 +0100 |
| commit | c671d8af0bb07b028d808b994b83b2ec25578a44 (patch) | |
| tree | 6b167c1835d62577ce589ebe5096a6621a8778c2 /board/toradex | |
| parent | 949b5a969d107613b61a1e5eaf9e43c75a97f42c (diff) | |
| download | u-boot-c671d8af0bb07b028d808b994b83b2ec25578a44.zip u-boot-c671d8af0bb07b028d808b994b83b2ec25578a44.tar.gz u-boot-c671d8af0bb07b028d808b994b83b2ec25578a44.tar.bz2 | |
board: colibri_imx7: reserve DDR memory for Cortex-M4
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for
the rpmsg communication. Both use cases need a fixed location of
memory reserved. For the rpmsg use case the reserved area needs
to be in sync with the kernel's hardcoded vring descriptor location.
Use the linux,usable-memory property to carve out 1MB of memory
in case the M4 core is running. Also make sure that the i.MX 7
specific rpmsg driver does not get loaded in case we do not carve
out memory.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Diffstat (limited to 'board/toradex')
| -rw-r--r-- | board/toradex/colibri_imx7/colibri_imx7.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index c001316..b0914a9 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -333,6 +333,43 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY) + int up; + + up = arch_auxiliary_core_check_up(0); + if (up) { + int ret; + int areas = 1; + u64 start[2], size[2]; + + /* + * Reserve 1MB of memory for M4 (1MiB is also the minimum + * alignment for Linux due to MMU section size restrictions). + */ + start[0] = gd->bd->bi_dram[0].start; + size[0] = SZ_256M - SZ_1M; + + /* If needed, create a second entry for memory beyond 256M */ + if (gd->bd->bi_dram[0].size > SZ_256M) { + start[1] = gd->bd->bi_dram[0].start + SZ_256M; + size[1] = gd->bd->bi_dram[0].size - SZ_256M; + areas = 2; + } + + ret = fdt_set_usable_memory(blob, start, size, areas); + if (ret) { + eprintf("Cannot set usable memory\n"); + return ret; + } + } else { + int off; + + off = fdt_node_offset_by_compatible(blob, -1, + "fsl,imx7d-rpmsg"); + if (off > 0) + fdt_status_disabled(blob, off); + } +#endif #if defined(CONFIG_FDT_FIXUP_PARTITIONS) static const struct node_info nodes[] = { { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ |