diff options
| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-02-14 19:35:34 +0200 |
|---|---|---|
| committer | Tom <twarren@nvidia.com> | 2023-02-23 12:55:37 -0700 |
| commit | 5668c75ce97d9209d4a0d193b16791a100cc99a8 (patch) | |
| tree | bf010da805d2bf3604bf0d7a21206aceb4439f4b /board/toradex/apalis_t30 | |
| parent | e7184debf4c2f35518811990473103793a1f639d (diff) | |
| download | u-boot-5668c75ce97d9209d4a0d193b16791a100cc99a8.zip u-boot-5668c75ce97d9209d4a0d193b16791a100cc99a8.tar.gz u-boot-5668c75ce97d9209d4a0d193b16791a100cc99a8.tar.bz2 | |
board: tegra30: switch to updated pre-dm i2c write
Configure PMIC voltages for early stages using updated
early i2c write.
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Diffstat (limited to 'board/toradex/apalis_t30')
| -rw-r--r-- | board/toradex/apalis_t30/Makefile | 2 | ||||
| -rw-r--r-- | board/toradex/apalis_t30/apalis_t30-spl.c | 34 |
2 files changed, 36 insertions, 0 deletions
diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile index 0ea3d8f..eed6070 100644 --- a/board/toradex/apalis_t30/Makefile +++ b/board/toradex/apalis_t30/Makefile @@ -1,4 +1,6 @@ # Copyright (c) 2014 Marcel Ziswiler # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_SPL_BUILD) += apalis_t30-spl.o + obj-y += apalis_t30.o diff --git a/board/toradex/apalis_t30/apalis_t30-spl.c b/board/toradex/apalis_t30/apalis_t30-spl.c new file mode 100644 index 0000000..6e54464 --- /dev/null +++ b/board/toradex/apalis_t30/apalis_t30-spl.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +/* I2C addr is in 8 bit */ +#define TPS65911_I2C_ADDR 0x5A +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} |