diff options
author | Ilko Iliev <iliev@ronetix.at> | 2021-04-16 15:48:13 +0200 |
---|---|---|
committer | Stefano Babic <sbabic@denx.de> | 2021-05-02 12:46:54 +0200 |
commit | fdd2f359e4b896993b6cfeb260267035d1d5c8c9 (patch) | |
tree | d485ce210b28a01e2598990d5e4b827111f88375 /board/ronetix | |
parent | dd8c32410e47880961a867ab143e48183b4c0493 (diff) | |
download | u-boot-fdd2f359e4b896993b6cfeb260267035d1d5c8c9.zip u-boot-fdd2f359e4b896993b6cfeb260267035d1d5c8c9.tar.gz u-boot-fdd2f359e4b896993b6cfeb260267035d1d5c8c9.tar.bz2 |
imx: Add support for Ronetix's iMX7-CM board
Console boot log:
U-Boot SPL 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200)
Trying to boot from MMC1
U-Boot 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200)
CPU: Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz)
CPU: Commercial temperature grade (0C to 95C) at 44C
Reset cause: POR
Model: Ronetix iMX7-CM Board
Board: iMX7-CM
DRAM: 512 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC: FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Net:
Warning: ethernet@30be0000 (eth0) using random MAC address - fe:be:37:01:5a:3f
eth0: ethernet@30be0000
Hit any key to stop autoboot: 0
Signed-off-by: Ilko Iliev <iliev@ronetix.at>
Diffstat (limited to 'board/ronetix')
-rw-r--r-- | board/ronetix/imx7-cm/Kconfig | 15 | ||||
-rw-r--r-- | board/ronetix/imx7-cm/MAINTAINERS | 6 | ||||
-rw-r--r-- | board/ronetix/imx7-cm/Makefile | 8 | ||||
-rw-r--r-- | board/ronetix/imx7-cm/README | 11 | ||||
-rw-r--r-- | board/ronetix/imx7-cm/imx7-cm.c | 98 | ||||
-rw-r--r-- | board/ronetix/imx7-cm/spl.c | 156 |
6 files changed, 294 insertions, 0 deletions
diff --git a/board/ronetix/imx7-cm/Kconfig b/board/ronetix/imx7-cm/Kconfig new file mode 100644 index 0000000..a4bc48f --- /dev/null +++ b/board/ronetix/imx7-cm/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX7_CM + +config SYS_BOARD + default "imx7-cm" + +config SYS_VENDOR + default "ronetix" + +config SYS_SOC + default "mx7" + +config SYS_CONFIG_NAME + default "imx7-cm" + +endif diff --git a/board/ronetix/imx7-cm/MAINTAINERS b/board/ronetix/imx7-cm/MAINTAINERS new file mode 100644 index 0000000..184c887 --- /dev/null +++ b/board/ronetix/imx7-cm/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX7-CM BOARD +M: Ilko Iliev <iliev@ronetix.com> +S: Maintained +F: board/ronetix/imx7_cm/ +F: include/configs/imx7_cm.h +F: configs/imx7_cm_defconfig
\ No newline at end of file diff --git a/board/ronetix/imx7-cm/Makefile b/board/ronetix/imx7-cm/Makefile new file mode 100644 index 0000000..7e08f23 --- /dev/null +++ b/board/ronetix/imx7-cm/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2017 NXP Semiconductors + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += imx7-cm.o +endif diff --git a/board/ronetix/imx7-cm/README b/board/ronetix/imx7-cm/README new file mode 100644 index 0000000..43e8c4f --- /dev/null +++ b/board/ronetix/imx7-cm/README @@ -0,0 +1,11 @@ +U-Boot for the Ronetix i.MX7-CM board + +Build U-Boot +============ +$ make imx7_cm_defconfig +$ make + +Burn the images to a SD card +============================ +$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync +$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1k seek=69; sync diff --git a/board/ronetix/imx7-cm/imx7-cm.c b/board/ronetix/imx7-cm/imx7-cm.c new file mode 100644 index 0000000..c23097f --- /dev/null +++ b/board/ronetix/imx7-cm/imx7-cm.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Ronetix GmbH + */ + +#include <init.h> +#include <net.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx7-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/gpio.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/io.h> +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, rev; + + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) { + puts("No pmic\n"); + return 0; + } + if (ret != 0) + return ret; + + reg = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 1.025V */ + reg = 0xd; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* decrease SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(975); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} + +static int setup_fec(void) +{ + return set_clk_enet(ENET_125MHZ); +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_fec(); + + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ + puts("Board: iMX7-CM\n"); + return 0; +} diff --git a/board/ronetix/imx7-cm/spl.c b/board/ronetix/imx7-cm/spl.c new file mode 100644 index 0000000..d36f734 --- /dev/null +++ b/board/ronetix/imx7-cm/spl.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Ronetix GmbH + * + * Author: Ilko Iliev <iliev@ronetix.at> + */ + +#include <common.h> +#include <cpu_func.h> +#include <init.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx7-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-mx7/mx7-ddr.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/gpio.h> +#include <fsl_esdhc_imx.h> +#include <spl.h> + +static struct ddrc ddrc_regs_val = { + .mstr = 0x01040001, + .rfshtmg = 0x00400046, + .init1 = 0x00690000, + .init0 = 0x00020083, + .init3 = 0x09300004, + .init4 = 0x04080000, + .init5 = 0x00100004, + .rankctl = 0x0000033F, + .dramtmg0 = 0x09081109, + .dramtmg1 = 0x0007020d, + .dramtmg2 = 0x03040407, + .dramtmg3 = 0x00002006, + .dramtmg4 = 0x04020205, + .dramtmg5 = 0x03030202, + .dramtmg8 = 0x00000803, + .zqctl0 = 0x00800020, + .dfitmg0 = 0x02098204, + .dfitmg1 = 0x00030303, + .dfiupd0 = 0x80400003, + .dfiupd1 = 0x00100020, + .dfiupd2 = 0x80100004, + .addrmap4 = 0x00000F0F, + .odtcfg = 0x06000604, + .odtmap = 0x00000001, + .rfshtmg = 0x00400046, + .dramtmg0 = 0x09081109, + .addrmap0 = 0x0000001f, + .addrmap1 = 0x00080808, + .addrmap4 = 0x00000f0f, + .addrmap5 = 0x07070707, + .addrmap6 = 0x0f0f0707, +}; + +static struct ddrc_mp ddrc_mp_val = { + .pctrl_0 = 0x00000001, +}; + +static struct ddr_phy ddr_phy_regs_val = { + .phy_con0 = 0x17420f40, + .phy_con1 = 0x10210100, + .phy_con4 = 0x00060807, + .mdll_con0 = 0x1010007e, + .drvds_con0 = 0x00000d6e, + .cmd_sdll_con0 = 0x00000010, + .offset_lp_con0 = 0x0000000f, + .offset_rd_con0 = 0x0a0a0a0a, + .offset_wr_con0 = 0x06060606, +}; + +static struct mx7_calibration calib_param = { + .num_val = 5, + .values = { + 0x0E407304, + 0x0E447304, + 0x0E447306, + 0x0E447304, + 0x0E447304, + }, +}; + +static void ddr_init(void) +{ + mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, &calib_param); +} + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void uart1_pads_set(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +void board_init_f(ulong dummy) +{ + arch_cpu_init(); + + uart1_pads_set(); + + timer_init(); + + preloader_console_init(); + + ddr_init(); + + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} + +void reset_cpu(void) +{ +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_PUS_PU47KOHM) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +void usdhc1_pads_set(void) +{ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); +} + +static struct fsl_esdhc_cfg usdhc_cfg = { + USDHC1_BASE_ADDR, 0, 4 +}; + +int board_mmc_init(struct bd_info *bis) +{ + usdhc1_pads_set(); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} |